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Logic design of asynchronous circuits

Logic design of asynchronous circuits. Part II: Logic synthesis from concurrent specifications. Outline. Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit Complex gates

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Logic design of asynchronous circuits

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  1. Logic design ofasynchronous circuits Part II: Logic synthesis fromconcurrent specifications

  2. Outline • Overview of the synthesis flow • Specification • State graph and next-state functions • State encoding • Implementability conditions • Speed-independent circuit • Complex gates • C-element architecture ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  3. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  4. Specification x x y y z z z+ x- x+ y+ z- y- Signal Transition Graph (STG) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  5. x y z z+ x- x+ y+ z- y- Token flow ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  6. xyz 000 x+ 100 y+ z+ z+ x- 110 101 x- x+ y+ z- y- y+ z+ 001 111 y- y+ x- 011 z- 010 State graph ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  7. xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 Next-state functions ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  8. Gate netlist x y z ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  9. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  10. Bus Data Transceiver DSr LDS Device D LDTACK DSr LDS VME Bus Controller DSw LDTACK D DTACK DTACK Read Cycle VME bus ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  11. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  12. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  13. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  14. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  15. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  16. Circuitsynthesis • Goal: • Derive a hazard-free circuitunder a given delay model andmode of operation ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  17. Speed independence • Delay model • Unbounded gate / environment delays • Certain wire delays shorter than certain paths in the circuit • Conditions for implementability: • Consistency • Complete State Coding • Persistency ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  18. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  19. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  20. LDS + LDS = 0 LDS - LDS = 1 Binary encoding of signals DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  21. 01100 00110 Binary encoding of signals 10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ DSr+ DTACK- 10110 01110 10110 D+ D- DTACK+ DSr- (DSr , DTACK , LDTACK , LDS , D) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  22. ER (LDS+) LDS+ QR (LDS-) LDS- LDS- LDS- ER (LDS-) QR (LDS+) Excitation / Quiescent Regions ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  23. LDS+ LDS- LDS- LDS- 10110 10110 Next-state function 0  1 0  0 1  1 1  0 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  24. DTACK DSr DTACK DSr D LDTACK D LDTACK 00 00 01 01 11 11 10 10 00 00 01 01 11 11 10 10 Karnaugh map for LDS LDS = 1 LDS = 0 - - - 0 0 - 1 1 - - - - - - - - 1 1 1 - - - - - 0 0 - 0 0 0 - 0/1? ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  25. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  26. DSr+ DSr+ DSr+ Concurrency reduction LDS+ LDS- LDS- LDS- 10110 10110 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  27. Concurrency reduction DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  28. State encoding conflicts LDS+ LDTACK- LDS- LDTACK+ 10110 10110 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  29. CSC+ CSC- Signal Insertion LDS+ LDTACK- LDS- LDTACK+ 101101 101100 D- DSr- ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  30. Design flow Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  31. Complex-gate implementation ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  32. Implementability conditions • Consistency • Rising and falling transitions of each signal alternate in any trace • Complete state coding (CSC) • Next-state functions correctly defined • Persistency • No event can be disabled by another event (unless they are both inputs) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  33. Implementability conditions • Consistency + CSC + persistency • There exists a speed-independent circuit that implements the behavior of the STG(under the assumption that ay Boolean function can be implemented with one complex gate) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  34. a- c+ a 100 000 001 b c b+ b+ Persistency a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  35. a+ 0000 a+ b+ 1000 b+ 1100 a- a- 0100 c+ c+ 0110 d+ d- d+ 0111 a+ a+ 1111 b- b- 1011 a- c- a- c- 0011 1001 a- c- d- 0001

  36. ab 0000 cd 00 01 11 10 a+ 1000 0 0 0 0 00 b+ 1100 1 0 a- 01 0100 c+ 1 1 1 1 0110 11 d- d+ 0111 1 10 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ER(d+) ER(d-)

  37. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 Complex gate

  38. S z C R Implementation with C elements • • •  S+  z+  S-  R+  z-  R-  • • • • S (set) and R (reset) must be mutually exclusive • S must cover ER(z+) and must not intersect ER(z-)  QR(z-) • R must cover ER(z-) and must not intersect ER(z+)  QR(z+) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  39. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 S d C R

  40. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 but ... S d C R

  41. Assume that R=ac has an unbounded delay 0000 a+ 1000 b+ 1100 a- 0100 c+ R+ disabled (potential glitch) 0110 d- d+ 0111 a+ 1111 b- 1011 a- c- 0011 1001 a- c- 0001 Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; S d C R

  42. 0000 a+ 1000 b+ 1100 a- 0100 c+ 0110 d- d+ 0111 a+ 1111 b- 1011 S a- c- d 0011 1001 C R a- c- 0001 ab cd 00 01 11 10 0 0 0 0 00 1 0 01 1 1 1 1 11 1 10 Monotonic covers

  43. S d C R C-based implementations c d C b a c weak c d weak d a a b generalized C elements (gC) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  44. Speed-independent implementations • Implementability conditions • Consistency • Complete state coding • Persistency • Circuit architectures • Complex (hazard-free) gates • C elements with monotonic covers • ... ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  45. y- y- 1001 z- w- 1000 0001 w+ y+ w- z- x+ z- w- w+ 1010 0000 0101 w- y+ x+ z- y+ x+ x- 0010 0100 x- x+ y+ z+ 0110 z+ Synthesis exercise 1011 0011 0111 Derive circuits for signals x and z (complex gates and monotonic covers) ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  46. y- 1001 z- w- 1000 0001 w+ y+ w- z- x+ 1010 0000 0101 w- y+ x+ z- 0010 0100 x- x+ y+ z+ 0110 Synthesis exercise 1011 wx yz 00 01 11 10 - 1 0 1 00 0011 - 1 0 1 01 - 0 0 0 11 - 1 1 0 10 0111 Signal x ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

  47. y- 1001 z- w- 1000 0001 w+ y+ w- z- x+ 1010 0000 0101 w- y+ x+ z- 0010 0100 x- x+ y+ z+ 0110 Synthesis exercise 1011 wx yz 00 01 11 10 - 0 0 0 00 0011 - 0 0 0 01 - 1 1 1 11 - 1 0 0 10 0111 Signal z ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

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