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HW/SW SystemC Co-Simulation SoC Validation Platform

HW/SW SystemC Co-Simulation SoC Validation Platform. Thomas Schuster. Outline. 1. Introduction TU Braunschweig/IDA 2. Study Objectives & Organization 3. Virtual Platform Infrastructure 4. Development of TLM 2.0 Simulation Models 5. Proof-of-concept VP.

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HW/SW SystemC Co-Simulation SoC Validation Platform

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  1. HW/SW SystemC Co-Simulation SoC Validation Platform Thomas Schuster

  2. Outline 1. Introduction TU Braunschweig/IDA 2. Study Objectives & Organization 3. Virtual Platform Infrastructure 4. Development of TLM 2.0 Simulation Models 5. Proof-of-concept VP

  3. 1. TECHNISCHE UNIVERSITÄTBRAUNSCHWEIG 14.000 Students 3.000 University staff 1.600 Scientists 5 Departments 40 Degree Programs Founded in 1745 (oldest university of technology in Germany) School of Carl-Friedrich Gauß

  4. IDA Institute of Computer and Communication Network Engineering Institute of Computer and Communication Network Engineering director: Prof. Rolf Ernst communication networks embedded computers for space applications VLSI systems design Prof. Mladen Berekovic sponsored by Intel computer aided embedded system design Prof. Admela Jukan Prof. RolfErnst Prof. Harald Michalik cryptography Prof. Wael Adi • ca. 60 employees (21 univ. funded) • ca. 2.2 Mio. € 3rd party funding in 2006 • part of department of EE&IT staff system administration mechanical lab electronic lab accounting secretariat

  5. People involved IDA: Prof. Dr. Harald Michalik Study Management Prof. Dr. Mladen Berekovic Chief Technical Scientist Thomas Schuster Study Engineer Dennis Bode Study Engineer Bjoern Osterloh Study Engineer ESA Supervisors: Dr. Luca Fossati Dr. Laurent Hili

  6. 2. Project Objectives • High-Level modeling of key IPs in TLM 2.0 • Functional validation and timing accuracy analysis • Power Modeling • Definition of a design flow for VP modeling • Selection of appropriate infrastructure • Development of a proof-of-concept Virtual Platform • Demonstration of a design space exploration www.vlsilab.org

  7. Study Organization Jan 2010 today July 2011

  8. Virtual Platform / Advantages A Virtual Platform is an abstract hardware model that is simulated by software. VPs can easily be duplicatedand packaged allowing multiple developers to work in parallel. Software development can start before hardware prototypes are available. Productivity Availability Accessibility Consistency Unlike physical hardware VPs provide observability and controllability for the entiresystem. VPs can be co-simulated/emulated. Gradual refinement from high abstraction to RTL eases verification.

  9. 3. Selection of VP Infrastructure • Requirements: • Open Source (GPL, L-GPL) • Support for TLM 2.0 (LT and AT) • Concept for development of: • - memory mapped devices • - complex bus models • Vendor tool independence • System shall be developed around TRAP (Transaction level Automatic Processor generator) http://code.google.com/p/trap-gen/

  10. Survey on Tools & Techniques Open Tools for TLM 2.0 are hard to find.

  11. is closest to requirements • Mission: • Provision of vendor-independent infrastructure • Open platform for joint IP development • Infrastructure (selected): • GreenBus - Foundation for Bus Modeling with TLM 2.0 • (incl. AMBA impl. almost ready-to-use) • GreenReg - Framework for Register & Device Modeling • GreenControl - Control and Configuration Interfaces (CCI) • GreenScript - Methods and Tools for Use-Case capture • … and much more, see: www.greensocs.com

  12. GreenSocs System Overview Source: Mark Burton, GreenSocs

  13. 4. Modeling of SystemC IP Models will be implemented in LT and AT flavor of TLM 2.0

  14. Transaction Level Modeling Function calls through dedicated interfaces model synchronization of concurrent threads of execution. TLM 2.0 Loosely Timed (LT) – blocking communication, temporal decoupling TLM 2.0 Approximately Timed (AT)– non-blocking communication 2 Phase AT (begin request, end response) 4 Phase AT (begin/end request, begin/end response) n Phase AT Accuracy Simulation Performance Cycle Accurate SystemC or RTL simulation

  15. Device Modeling with GreenReg GreenReg Protocol (Socket) Register Set User Model Regfile callbacks reg reg reg behavior timing power Example Slave Module • Registers can be automatically hooked on sockets • Registers provide Pre/Post Read/Write callbacks to behavior

  16. Verification of IP Models Full TLM Simulation Reference Simulation (TLM/RTL) test vectors test vectors TLM Stimuli/Monitor TLM Stimuli/Monitor AMBA AMBA TLM Design Under Test TLM/RTL Adapter RTLDesign Under Test Models will be evaluated with respect to simulation performance & accuracy.

  17. 5. Proof-of-Concept VP MEM Segmented AHB 2x4 LEON processors Aeroflex MCTRL Status/Ctrl Regs MEM Aeroflex IRQMP CAN SpaceWire SoC Wire AMBA Aeroflex GPTimer Aeroflex GPTimer Aeroflex GPTimer Aeroflex GPTimer Aeroflex GPTimer Aeroflex GPTimer MEM Bridge Bridge Mem Aeroflex GPTimer Aeroflex GPTimer AMBA AMBA LEON3 LEON3 LEON3 LEON3 LEON3 LEON3 LEON3 LEON3 Cache Cache Cache Cache Cache Cache Cache Cache MMU MMU MMU MMU MMU MMU MMU MMU Multi-Processor system stimulating all IPs generated in the course of the project.

  18. GNU Compiler Collection + Embedded C library Real-Time Executive for Multi-processor Systems Platform Software Architecture Open Source Software Architecture: Compiler OS A set of MiBench applications will be executed on top of RTEMS:

  19. HW/SW SystemC Co-Simulation Platform Thank you for your attention!

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