JAZiO ™ Supplemental Information

1. JAZiO™ Supplemental Information

2. Alternating References VTR VREF Data Input Pseudo Differential Data Input JAZiO Instead of static VREF, JAZiO uses dynamic Voltage/Timing Reference (VTR) • Larger differential signal when signal changes • Reduces signal slew rate to achieve the same differential swing

3. D Voh pp Vref D Vol Voltage to Time Domain Transposition Above or Below Reference Peak to Peak Difference Change vs No Change Gap Change No Change Pseudo Differential Full Differential JAZiO JAZiO transposes the voltage domain to the time domain, since signal binary is defined in the time domain. JAZiO binary margin is more dependent on transition time rather than voltage swing.

4. This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.). Data In 3 Comp A Data In 1 1 VTR VTR Change Change No Change • Case 3: Comp A remains High (weakly) while the Data Output retains the previous data • The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output Change /No Change Concept Comp A • Case 1: Comp A amplifies the change and the data passes through the Steering Logic

5. Current Single Ended Technologies I/O Interface Power Comparison 5000 I/O Power For 15pf & 30pf Load Cap. @ 1.8V Vtt 4500 The system can be optimized to achieve: Cost reduced package and lower system cost or Higher integration: more pins for more performance. 4000 3500 3000 Power (mW) 2500 2000 1500 1000 (x16) JAZiO™ (x16) 500 JAZiO-2000 JAZiO-1000 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 Giga Bytes/Second

6. Better I/O Interface Transition Time Comparison 10G JAZiO™ • Reduced noise • Improved margins • Improved scalability 1G RDRAM Bits per Second per Pin (b/S) DDR DDR 100M SDRAM-100 SDRAM EDO 10M 6.4 3.2 1.6 0.8 0.4 0.2 0 Transition Time (nS)

7. Noise • JAZiO works best with slow edges (use the entire Bit Time!) • JAZiO works with small transition levels (differential sensing) • Works with any Termination Scheme (Series, Parallel, Single, Dual, Source and even none in some applications) • JAZiO is entirely common-mode

8. Power Supply Noise Issues Common Mode VTT Common Mode VTT JAZiO Signal VTR Common Mode Noise Sources VTT Common Mode VTT Signal Pseudo Differential VREF Noise Sources Noise Sources • VSSQ noise between signal and VREF • VTT noise and/or VTT mismatch on either end • VREF impedance to Signal impedance mismatch

9. Environmental Noise Issues VTT VTT JAZiO Signal VTR VTT VTT Pseudo Differential Signal VREF • Slower transition generates less noise in JAZiO • Smaller transition generates less noise in JAZiO • VTRs are isolated by VSS to eliminate noise variations Board dimensions have not shrunk as rapidly as on-chip dimensions

10. Environmental Noise Issues No Change (Low Victim) JAZiO 0.5V 2 On Hard 1 CASE 1 Narrower Band Less Noise; More Signal More Noise; Less Signal Wider Band Change (High to Low Victim) 1 VREF Pseudo Differential 0.8V 2 Slowly Turn On CASE 2 Noise (Change) Noise (No Change) No Noise (No Change) No Noise (Change)

11. L2 CPU Controller DRAM DRAM JAZiO JAZiO JAZiO DRAM Application Example JAZiO can be used between Controller and DRAM to achieve even greater than 2 GBit/pin/sec bandwidth JAZiO’s signaling technology allows bus expansion in both depth and width. No restriction on bus protocol or definition JAZiO is a low latency interface JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. Single cycle power-up initialization allows user to fully utilize standby/sleep mode Low power and wide operating frequency improves DRAM cost JAZiO’s small voltage swing and slow transition time allows multiple slots with terminations at both ends. Easily adaptable for large memory systems (like servers) Better performance and scalability

12. Lower Address & Control Lines Upper Address & Control Lines VTT 5 Bit Addr & Ctrl VTR0 VTR0 & VTR0 VTR0 VTT CONTROLLER VTT 5 Bit Addr & Ctrl VTT Clock Source Clock Data VTT VTR1 VTR1 & VTR1 VTR1 VTT VTT Data DRAM DRAM DRAM Upper Data Lines Lower Data Lines

13. 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2-Pins CLK 2-Pins VTR0 TCAC 2-Pins VTR1 RAS CS/RAS 1-Pin CS CS RAS TRCD CAS/WE 1-Pin CAS WE ADR 0:7/ ADR 8:15 Cols 8:15 8-Pins Rows 0:7 Rows 8:15 Cols 0:7 18 Pins I/O 0:17 TRCD ~20ns or 10 cycles TCAC ~20ns or 10 cycles Read Cycle 8-Bit Burst

14. 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2ns 2-Pins CLK VTR0 2-Pins TCWD VTR1 2-Pins RAS CS/RAS 1-Pin CS CS RAS WE TRCD CAS/WE 1-Pin CAS ADR 0:7/ ADR 8:15 Cols 8:15 8-Pins Rows 0:7 Rows 8:15 Cols 0:7 18 Pins I/O 0:17 TRCD ~20ns or 10 cycles TCWD ~20ns or 10 cycles Write Cycle 8-Bit Burst

15. Read, Read,Write, Read Burst 10 Cycles 10 Cycles 10 Cycles 10 Cycles CLK VTR0 VTR1 CS/RAS CAS/WE ADR 0:7/ ADR 8:15 I/O 0:17

16. Data Data Data Data Data 27:35 Data 18:26 DRAM DRAM VTT VTT VTR2 VTR2 & VTR2 VTR2 VTT CONTROLLER VTT Clock 5 Bit Addr & Ctrl VTT VTT Clock Source VTR0 VTR0 & VTR0 VTR0 VTT VTT 5 Bit Addr & Ctrl VTT Clock VTT VTR1 VTR1 & VTR1 VTR1 VTT VTT Lower Address & Control Lines DRAM DRAM Upper Address & Control Lines Data 0:8 Data 9:17

17. L2 CPU JAZiO JAZiO Controller DRAM DRAM CPU to SRAM Application Example JAZiO can be used between CPU and SRAM (L2) to achieve huge bandwidth and low latency JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin) Might use no terminations due to slow transitions and short lengths Control pin count on Back Side Bus Easily adaptable to support multiple cache sizes More external cache, less internal cache  smaller CPU die sizes No restriction and full differentiation on bus protocol and definition Better performance and scalability

18. L2 CPU JAZiO JAZiO Northbridge DRAM DRAM Front Side Bus JAZiO can be used in a proprietary bus between CPU and the Northbridge to achieve even greater than 16 GBytes/sec bandwidth. JAZiO bus can essentially run at the same frequency as the internal CPU clock with DDR. No restriction and full differentiation on bus protocol and definition. Lower cost in packaging and heat sink requirements due to reduced pins and power. Better performance and scalability.

19. JAZiO JAZiO Front Side Bus JAZiO can be used in a proprietary bus between CPU(s) and the Controller(s) to achieve many GBytes/sec bandwidth No restriction and full differentiation on bus protocol and definition MP snoopy bus or very high speed point-to-point For point-to-point, JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin) Keep pin count growth and bus power under control Lower cost in packaging and heat sink requirements due to reduced pins and power Better performance and scalability L2 CPU Controller DRAM DRAM

20. JAZiO JAZiO JAZiO Internal Application Example (SOC, Embedded, Etc.) JAZiO is well suited for large internal bus structures (SOC), which have greater than 2 pf/line loading. JAZiO uses ~0.3V swing with small transmitters and receivers to easily substitute traditional full swing buses. JAZiO also scales as the technology changes (process, voltage, etc.). JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. JAZiO requires no PLL or DLL or repeater circuitry. JAZiO can support multiple frequencies on a given bus structure, it can be used synchronously or asynchronously, can support multiple supply voltages on the same bus, thus allowing the user flexibility in optimizing any implementation.