1 / 41

CPU12 (Programming Model)

CPU12 (Programming Model). MC9S12DP256. SCI 1. SCI 0. ATD 0. ATD 1. 12K SRAM. 256K FLASEEPROM. Internal Bus. SPI 2 or PWM CH 4-7. SPI 1 or PWM CH 0-3. SPI 0. BKP INT MMI. PWM 8 CHAN. HCS12 CPU. SIM. CM BDM MEBI.

dixon
Download Presentation

CPU12 (Programming Model)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CPU12(Programming Model)

  2. MC9S12DP256 SCI 1 SCI 0 ATD 0 ATD 1 12K SRAM 256K FLASEEPROM Internal Bus SPI 2 or PWM CH 4-7 SPI 1 or PWM CH 0-3 SPI 0 BKP INT MMI PWM 8 CHAN HCS12 CPU SIM CM BDM MEBI PLL PIT msCAN 4 or IIC msCAN 3 msCAN 2 msCAN 1 BDLC or msCAN 0 ECT 8 CHAN 4K BYTES EEPROM

  3. Features (1 of 2) • HCS12 has identical programmers model to M68HC11/M68HC12 • No new registers • No changes in interrupt stacking order • Muxed and non-muxed external interfaces • Can reuse existing software source code • Note: timing loops change due to new clock frequency, • Byte counts and instruction cycle times. • Performance improvement when using new instructions • Reduced interrupt latency • Increase math speed • Increase performance • Instruction Queue data to increase performance • Instructions execute faster while remaining deterministic

  4. Features (2 of 2) • Added instructions designed with compilers in mind: • New instructions and addressing modes to support high level languages.* • Added: • Stack pointer and program counter offset indexed addressing • 11 math instructions • Fuzzy logic instructions • Long branch instruction (16 bit offset) • Move instruction (memory to memory) • Min / max functions • Bit manipulations for entire memory map • Exchange / transfer • Table look-up and interpolate function • Looping construct * MC68HC12 and HCS12 have Identical Instruction Set.

  5. Programming Model 7 0 7 0 8-BIT ACCUMULATORS A AND B B A 0 15 D OR 16-BIT DOUBLE ACCUMULATOR 15 0 X INDEX REGISTER X 15 0 Y INDEX REGISTER Y 0 15 STACK POINTER SP 0 15 PROGRAM COUNTER PC 0 7 S X H I N Z V C CONDITION CODE REGISTER CARRY/BORROW FROM MSB OVERFLOW ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT 3) X-INTERRUPT MASK STOP DISABLE

  6. Condition Code Register S X H I N Z V C MASKING BITS ARITHMETIC BITS • Reflect results of instruction execution. C - Carry/Borrow from MSB S - Disables STOP instruction when set. unsigned arithmetic X - Masks XIRQ request when set. V - 2's complement overflow indication - set by hardware reset, cleared by software. signed arithmetic - set by unmaskable XIRQ Z - Zero result I - Masks interrupt request from all IRQ level sources ( both external and internal ) N - Negative ( follows MS Bit of result ) when set. - set by unmasked I level request H - Half Carry from bit 3 to bit 4 or unmasked XIRQ ADD operations only

  7. HCS12Addressing Modes

  8. HC11 Addressing Modes INHERENT CLRB IMMEDIATE LDAA #$12 EXTENDED LDAA $4000 DIRECT LDAA $50 INDEXED LDAB $10,X RELATIVE BNE LOOP

  9. HCS12 New Indexed Addressing Modes LDAA -$10,X Index 5-bit signed offset LDAA -$50,X Indexed 9-bit signed offset LDAA -$500,X Indexed 16-bit signed offset JMP [D,X] Indexed Memory Indirect

  10. Indexed 5-Bit Signed Offset X 1000 + 5-BIT OFFSET A 1 2 1 2 LDAA $6,X STAA -$8,Y 1 2 + 5-BIT OFFSET Y 2000 • 5 Bit offset is signed included in instruction post byte. • X, Y, SP or PC register can be used for indexing. • Offset range from -16 to +15 from base register.

  11. Indexed 9-Bit Signed Offset (IDX1) X 1000 + 9-BIT OFFSET A A A A A LDAA $70,X STAA -250,Y A A + 9-BIT OFFSET Y 2000 • 9 BIT OFFSET IS SIGNED INCLUDED IN EXTENSION BYTE FOLLOWING INSTRUCTION. • X, Y, SP OR PC REGISTER CAN BE USED FOR INDEXING. • OFFSET RANGE FROM -256 TO +255 FROM BASE REGISTER.

  12. Indexed 16-Bit Offset (IDX2) X 2000 + 16-BIT OFFSET A B B B B LDAA $700,X STAA -$5000,Y B B + 16-BIT OFFSET Y A000 • 16- Bit offset provided in two extension post bytes. • X, Y, SP OR PC register can be used for indexing. • Offset Range + or - 32KBytes from base register.

  13. Indexed 16-Bit Indirect Offset ([IDX2]) X 3000 + 16-BIT INDIRECT OFFSET 6150 $3500 LDD [$500,X] D 1234 1234 <EA> $6150 • 16- Bit indirect offset added to base register to form <ea> of the operand. • X, Y, SP or PC register can be used for indexing. • Offset range + or - 32k bytes from base register.

  14. E 0 0 0 PC 9800 Indexed - D-Indirect ([D,IDX]) X 1000 D + 3000 $4000 JMP [D,X] 9 8 0 0 <EA> = E000 • D- Accumulator added to base register to form <ea> of indirect address. • X, Y, SP or PC register can be used for indexing. • Offset range + or - 32KBytes from base register.

  15. Indexed- Accumulator Offset SP 1000 + 60 A B 9 9 9 9 $1060 LDAA B,SP • The Accumulator maybe A, B OR 16-bit D . • X, Y, SP or PC register can be used for indexing. • Offset range up to + or - 32KBytes from base register.

  16. Indexed - Pre/Post Decrement/Increment MOVW 2 ,X+ ,2,Y+ AFTER BEFORE X X 2000 5 6 2002 AFTER Y Y 3000 3002 5 6 Other examples: MOVW 8,X+, 8,-Y MOVW 2,X+ ,4,+Y STAA 1,-SP STAA 4,SP+

  17. Relative Addressing • Only for Branch Instructions. (L)BEQ LOOP LOOP OCL Bcc OP CODE PC OFFSET OFFSET + OFFSET + Bcc OP CODE OCL OFFSET LOOP PC • Branch Instructions are 2 or 4 bytes in length. • All Branches are taken from the next instruction address (Destination of branch is calculated by adding signed offset byte to OCL +2 OR +4 )

  18. HCS12 Instruction set

  19. INSTRUCTION SET Data Handling Arithmetic Logic Data Test Branch Jump & Subroutine Calls

  20. DATA HANDLING INSTRUCTIONS(DATA MOVEMENT) MOVE MOV MEM MEM EXAMPLE: MOVW 2,X+ , 2,-Y

  21. STACK OPERATION EXAMPLE: PSHX BEFORE PSHX AFTER MEM MEM B7 B0 B7 B0 INCREASING ADDRESSES INCREASING ADDRESSES $3FFE SP • XH • XL • TOP OF STACK $3FFF SP TOP OF STACK $4000 $4000 SP SP

  22. DATA HANDLING INSTRUCTIONS(TRANSFER AND EXCHANGE) FUNCTION MNEMONIC OPERATION TBA B A • TRANSFER DATA • TRANSFER REG TO REG TFR A, B, CCR, D, X, Y, SP • A, B, CCR, D, X, Y, SP • EXCHANGE EXG A, B, CCR, D, X, Y, SP • A, B, CCR, D, X, Y, SP TAB A B TXS R SP TYS TSY SP R TSX D X D Y EXCHANGE DATA XGDX XGDY EXAMPLE1: TFR X ,A EXAMPLE2: EXG Y ,B

  23. DATA HANDLING INSTRUCTIONS(ALTER DATA) FUNCTION MNEMONIC OPERATION DECREMENT DEC (M)-1 (M) DECA A-1 A DECB B-1 B X-1 X DEX Y-1 Y DEY S-1 S DES INCREMENT INC (M)+1 (M) INCA A+1 A INCB B+1 B INX X+1 X INY Y+1 Y INS S+1 S

  24. DATA HANDLING INSTRUCTIONS(ALTER DATA) FUNCTION MNEMONIC OPERATION COMPLEMENT, 2'S NEG 0-(M) (M) (NEGATE) NEGA 0-A A NEGB 0-B B COMPLEMENT, 1'S COM (M) (M) COMA A A COMB B B CLEAR CLR 0 (M) CLRA 0 A CLRB 0 B BIT(S) CLEAR BCLR (M) MASK (M) BIT(S) SET BSET (M) + MASK (M) • Bit Manipulation Example: BSET OFFSET,X, #MASK

  25. DATA HANDLING INSTRUCTIONS

  26. DATA HANDLING INSTRUCTIONS(SHIFT AND ROTATE) FUNCTION MNEMONIC OPERATION ROTATE LEFT ROL M ROLA A ROLB B C b7 b0 M ROTATE RIGHT ROR A RORA B RORB C b7 b0 M SHIFT LEFT, ASL(LSL) 0 A ARITHMETIC ASLA(LSLA) C b7 b0 B (LOGICAL) ASLB(LSLB) 0 A B D ASLD(LSLD) C b15 b0 SHIFT RIGHT, ASR M ARITHMETIC ASRA A ASRB B b7 b0 C SHIFT RIGHT, LSR M 0 LOGICAL LSRA A b0 C b7 LSRB B LSRD 0 A B D b15 b0 C

  27. DATA TEST INSTRUCTIONS FUNCTION MNEMONIC TEST BITA A (M) BIT TEST BITB B (M) COMPARE CBA A-B CMPA A-(M) CMPB B-(M) CPD R -(M+1) L CPX R -(M)-C H CPY COMPARE STACK CPS SP - ( M :M +1) TST (M)-0 TEST, ZERO OR TSTA A-0 MINUS TSTB B-0

  28. CONDITIONAL BRANCH INSTRUCTIONS (1 0F 3) MNEMONIC CONDITION CCR TEST INDICATION (L) BMI MINUS N=1 r=NEGATIVE (L) BPL PLUS N=0 r=POSITIVE *(L) BVS OVERFLOW V=1 r=SIGN ERROR *(L) BVC NO OVERFLOW V=0 r=SIGN OK *(L)BLT LESS A < M [N V]=1  *(L)BGE GREATER OR EQUAL A >= M [N V]=0  * (L)BLE LESS OR EQUAL A <= M [Z+(N V)]=1  *(L) BGT GREATER A > M [Z+(N V)]=0  Indication (L)BEQ refers to the EQUAL Z=1 A=M use of a (L) BNE CMPA M NOT EQUAL Z=0 A <> M instruction immediately (L)BHI HIGHER [C+Z]=0 A > M before the branch (L) BLS LOWER OR SAME [C+Z]=1 A <= M *Use for signed arithmetic only CARRY CLEAR C=0 A >= M (L)BCC (BHS) CARRY SET C=1 A < M (L) BCS (BLO)

  29. CONDITIONAL BRANCH INSTRUCTIONS (2 0F 3) FUNCTION MNEMONIC OPERATION DECREMENT & BRANCH DBEQ COUNTER - $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC DBNE COUNTER - $01, COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC INCREMENT & BRANCH IBEQ COUNTER + $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC • IBNE COUNTER + $01 COUNTER • IF COUNTER <>0, THEN (PC)+$0003 +REL PC • TBEQ IF COUNTER = 0, THEN PC+$0003 + REL PC • TBNE IF COUNTER <>0, THEN PC+$0003 + REL PC TEST & BRANCH

  30. OCL OP CODE OPERAND MASK BRANCH DISP. BRANCH IF BITS SET OR CLEAR (3 of 3) • SINGLE INSTRUCTION TO LOGICALLY "AND" MASK WITH OPERAND AND BRANCH IF BITS ARE EITHER SET OR CLEARED. • USEFUL FOR POLLING INTERRUPT STATUS FLAGS, AND FOR MAKING PROGRAM DECISIONS BASED ON BIT(S) VALUES. • BRANCH IS TAKEN FROM NEXT INSTRUCTION ADDRESS (OCL+4, 5, OR 6 ) BRSET (M) MASK SERVICE BRCLR • ADDESSING MODES ALLOWED ARE: DIR, EXT, IDX, IDX1 & IDX2.

  31. ARITHMETIC INSTRUCTIONS (1 of 4) MNEMONIC FUNCTION OPERATION A + (M) A ADD ADDA B + (M) B ADDB D + (M+1) D ; D + M + C D ADDD H H L L ADD ABA A + B A ACCUMULATORS ABX X + B X ABY Y + B Y ADCA ADD WITH CARRY A + M + C A ADCB B + M + C B DECIMAL ADJUST CONVERTS BINARY ADDITION OF DAA BCD CHARS INTO BCD FORMAT

  32. ARITHMETIC INSTRUCTIONS (2 of 4) FUNCTION MNEMONIC OPERATION A A – (M) SUBTRACT SUBA B – (M) B SUBB D – (M+1) D ; D – (M) – C D SUBD H L L H SUBTRACT SBA A – B A ACCUMULATORS A – (M) – C A SUBTRACT WITH SBCA B – (M) – C B CARRY SBCB MULTIPLY MUL A * B D EXTENDED MULTIPLY EMUL D * Y Y : D EXTENDED MULTIPLY EMULS D * Y Y : D SIGNED

  33. ARITHMETIC INSTRUCTIONS (3 of 4)DIVIDE INSTRUCTIONS OPERATION D REG / X REG RESULT QUOTIENT IS IN X REMAINDER IS IN D INTEGER DIVIDE IDIV/IDIVS RADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSB • EXTENDED DIVIDE 32-BIT BY 16-BIT ( [UN ]SIGNED) EDIV/EDIVS EDIV EXAMPLE: EDIV[ S ] OPERATION (Y:D)/ (X) Y; REMAINDER D V = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000 V = 1, IF RESULT > $7FFF FOR SIGNED, UNDEFINED IF DIVISOR IS $0000 C = 1, IF DIVISOR WAS $0000

  34. ARITHMETIC INSTRUCTIONS (4 of 4)FRACTIONAL DIVIDE INSTRUCTION FRACTIONAL DIVIDE FDIV RADIX POINT OF THE RESULT IS TO THE LEFT OF THE MSB IF NUMERATOR IS GREATER THAN OR EQUAL TO THE DENOMINATOR, THEN V FLAG IS SET. RESULT EXAMPLES: A RESULT OF 1 IS 1/$10000 WHICH IS .0001 A RESULT OF $C000 IS $C000/$10000 WHICH IS .75 A RESULT OF $FFFF IS $FFFF/$10000 WHICH IS .9999

  35. EXTENDED MULTIPLY AND ACCUMULATE(EMACS) OPERATION: (M : M ) * (M : M ) + M ~ M+3) M ~ M+3 (X) (X+1) (Y) (Y+1) 15 0 15 0 X Y EXAMPLE: EMACS $2500 (* 32-BIT RESULT *)

  36. A + (M) A B + (M) B LOGIC INSTRUCTIONS FUNCTION MNEMONIC OPERATION AND ANDA A (M) A ANDB ANDCC CCR MASK CCR B (M) B EXCLUSIVE OR EORA A (M) A EORB B (M) B INCLUSIVE OR ORAA ORAB ORCC CCR + MASK CCR

  37. Jump and Subroutine Call Instructions

  38. CONDITION CODE REGISTER INSTRUCTIONS MNEMONIC FUNCTION OPERATION 0 C CLEAR CARRY CLC 0 I CLEAR INTERRUPT MASK CLI 0 V CLEAR OVERFLOW CLV 1 C SET CARRY SEC 1 I SET INTERRUPT MASK SEI 1 V SET OVERFLOW SEV A CCR ACCUMULATOR A CCR TAP CCR A CCR ACCUMULATOR A TPA OR CONDITION CODE ORCC CCR + OPERAND AND CONDITION CODE ANDCC CCR ^ OPERAND

  39. BLOCK MOVE ROUTINE WRITE A BLOCK MOVE ROUTINE. THE ROUTINE COPIES DATA FROM MEMORY LOCATION $1000 TO MEMORY LOCATION $1100. THE ROUTINE WILL END WHEN A DATA BYTE WITH VALUE OF ZERO IS MOVED. SUGGESTED PROGRAM STEPS ORIGINATE DATA AT ADDRESS $1000. FORM TABLE OF DATA TO BE MOVED FORM CONSTANT BYTE OF ‘0’. PROGRAM BEGINS @$4000. 1. INIT SOURCE POINTER T0 $1000. 2. INIT DESTINATION POINTER TO $1100. 3. GET DATA FROM SOURCE ADDRESS. 4. WRITE DATA TO DESTINATION ADDRESS, 5. IF DATA MOVED = 0, GO TO STEP 9, ELSE GO TO 6. 6. INCREMENT SOURCE POINTER. 7. INCREMENT DESTINATION POINTER. 8. GO TO STEP 3. 9. STAY HERE. • WRITE YOUR PROGRAM HERE • ORG $1000 • SOURCE FCC ‘DATA TO MOVE’ • FCB 0 • ORG $4000 • LOOP • BEQ DONE • BRA LOOP • DONE BRA DONE

  40. CLEAR RAM ROUTINE Write a routine to clear the HCS12 RAM memory, assume RAM begins at $1000 and ends at $3FFF. CLRRAM_RTN: ; Initialize X pointer to start of RAM ($1000) LOOP: ; Clear memory pointed to by X register, Inc X ; Compare pointer with $4000 ; If pointer not equal, Branch to LOOP Done BRA Done ; End program here

More Related