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Several Topics on TDC and the Wave Union TDC implemented in FPGA

Several Topics on TDC and the Wave Union TDC implemented in FPGA. Wu, Jinyuan Fermilab LBNL, Mar. 2009. Features of FPGA TDC. Fast Turn Around: 10 - 20 min recompile time. Sufficiently Good Resolution: Delay line based: as good as 10ps. Low Cost at Small Volume:

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Several Topics on TDC and the Wave Union TDC implemented in FPGA

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  1. Several Topics on TDC and the Wave Union TDC implemented in FPGA Wu, Jinyuan Fermilab LBNL, Mar. 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  2. Features of FPGA TDC • Fast Turn Around: • 10 - 20 min recompile time. • Sufficiently Good Resolution: • Delay line based: as good as 10ps. • Low Cost at Small Volume: • 8ch are implemented in EP2C8T144C6 ($31.68). • Flexibility of DAQ Integration: • Trigger, event packing, serialization etc. can be integrated in the same device. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  3. FPGA TDC: a Single Chip Solution PMT In FPGA TDC VTH VB FPGA PMT In • The differential input of the FPGA is a comparator. • It is possible to directly interface analog signals. TDC DAQ TDC TDC TDC VTH Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  4. Actual Board and Circuit FPGA TDC DAQ TDC TDC Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  5. TDC Using FPGA Logic Chain Delay • In Cyclone II chips, carry chain in a (ripple) adder is used as the delay line. • The registers recodes each bit of the adder result. • A priority encoder follows the array. IN CLK Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  6. Two Major Issues Due ToDifferential Non-Linearity • Widths of bins are different and varies with supply voltage and temperature. • Some bins are ultra-wide due to LAB boundary crossing Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  7. Digital Calibration Using Twice-Recoding Method • Use longer delay line. • Some signals may be registered twice at two consecutive clock edges. IN N2-N1=(1/f)/Dt The two measurements can be used: • to calibrate the delay. • to reduce digitization errors. CLK Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  8. Digital Calibration Result 2nd TDC • Power supply voltage changes from 2.5 V to 1.8 V, (about the same as 100 oC to 0 oC). • Delay speed changes by 30%. • The difference of the two TDC numbers reflects delay speed. Corrected Time 1st TDC • Warning: This is only an average bin width calibration, not bin-by-bin. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  9. Histogram Based Auto Calibration • It provides a bin-by-bin calibration at certain temperature. • It is a turn-key solution (bin in, ps out) • It is semi-continuous (auto update LUT every 16K events) 16K Events DNL Histogram S LUT In (bin) Out (ps) Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  10. Good, However • Auto calibration solved some problems  • However, it won’t eliminate the ultra-wide bins  Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  11. Cell Delay-Based TDC + Wave Union Launcher The wave union launcher creates multiple logic transitions after receiving a input logic step. The wave union launchers can be classified into two types: • Finite Step Response (FSR) • Infinite Step Response (ISR) This is similar as filter or other linear system classifications: • Finite Impulse Response (FIR) • Infinite Impulse Response (IIR) Wave Union Launcher In CLK Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  12. Wave Union Launcher A (FSR Type) Wave Union Launcher A 0: Hold 1: Unleash In CLK Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  13. Wave Union Launcher A:Two Measurements in One Array 1: Unleash Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  14. 1 2 Sub-dividing Ultra-wide BinsImproving Sensitivity 1: Unleash • Plain TDC: • Max. bin width: 160 ps. • Average bin width: 60 ps. • Wave Union TDC A: • Max. bin width: 65 ps. • Average bin width: 30 ps. 1 2 Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  15. DNL Histogram S LUT In (bin) Out (ps) Auto Calibration for Wave Union TDC A • It is not possible and not necessary to control the relative timing of two edges precisely. • Use TN1+TN2 as input for calibration. 0 Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  16. - - Measurement Result forWave Union TDC A • Plain TDC: • delta t RMS width: 40 ps. • 25 ps single hit. • Wave Union TDC A: • delta t RMS width: 25 ps. • 17 ps single hit. Raw TDC + LUT Histogram 53 MHz Separate Crystal Wave Union Histogram Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  17. More Measurements • Two measurements are better than one. • Let’s try 16 measurements? Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  18. Wave Union Launcher B (ISR Type) Wave Union Launcher B 0: Hold 1: Oscillate In CLK Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  19. VCCINT =1.20V VCCINT =1.18V Wave Union Launcher B: Screen Dump 1 Hit 16 Measurements @ 400 MHz Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  20. Delay Correction The raw data contains: • U-Type Jumps: [48-63][16-31] • V-Type Jumps: other small jumps. • W-Type Jumps: [16-31][48-63] Delay Correction Process: • Raw hits TN(m) in bins are first calibrated into TM(m) in picoseconds. • Jumps are compensated for in FPGA so that TM(m) become T0(m) which have a same value for each hit. • Take average of T0(m) to get better resolution. The processes are all done in FPGA. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  21. The Test Module Data Output via Ethernet FPGA with 8ch TDC Two NIM inputs BNC Adapter to add delay @ 150ps step. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  22. Test ResultOn Board Signal RMS 9ps • Two independent crystals for: • Driving TDC • Creating test hits Wave Union TDC B Wave Union TDC B + Wave Union TDC B Wave Union TDC B - Wave Union TDC B Wave Union TDC B + Wave Union TDC B Wu, Jinyuan (jywu168@fnal.gov) Fermilab Wave Union TDC B

  23. Test ResultNIM Inputs RMS 10ps 140ps 0 1 2 Wave Union TDC B BNC adapters to add delays @ 140ps step. Wave Union TDC B + NIM/ LVDS Wave Union TDC B Wave Union TDC B - LeCroy 429A NIM Fan-out Wave Union TDC B NIM/ LVDS Wave Union TDC B + Wave Union TDC B Wu, Jinyuan (jywu168@fnal.gov) Fermilab Wave Union TDC B

  24. Performance Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  25. Some Deleted Slides • Resource usage in TDC depends on the measurement resolution strongly. • To improve resolution by a factor of 2 may increase resource usage by a factor of 4 with the same base design. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  26. Test Result (1) RMS 20ps 150ps BNC adapters to add delays @ 150ps step. 0 1 2 NIM/ LVDS Wave Union TDC B LeCroy 429A NIM Fan-out - NIM/ LVDS Wave Union TDC B Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  27. Test Result (2) RMS 14ps 150ps 0 2 1 NIM/ LVDS Wave Union TDC B + Wave Union TDC B LeCroy 429A NIM Fan-out - NIM/ LVDS Wave Union TDC B + Wu, Jinyuan (jywu168@fnal.gov) Fermilab Wave Union TDC B

  28. Test Result (3) RMS 10ps 140ps 0 1 2 Wave Union TDC B Wave Union TDC B + NIM/ LVDS Wave Union TDC B Wave Union TDC B - LeCroy 429A NIM Fan-out Wave Union TDC B NIM/ LVDS Wave Union TDC B + Wave Union TDC B Wu, Jinyuan (jywu168@fnal.gov) Fermilab Wave Union TDC B

  29. Slower But Cheaper • Multi-sampling TDC uses significantly less resources. • Typical resolution is 500ps-1ns (LSB) or 144-288ps (RMS). • This scheme is suitable for drift chamber applications. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  30. Clock Domain Changing Multi-Sampling TDC FPGA Multiple Sampling Q3 QF c0 c0 QE Q2 • Ultra low-cost: 48 channels in $18.27 EP2C5Q208C7. • Sampling rate: 360 MHz x4 phases = 1.44 GHz. • LSB = 0.69 ns. c90 QD Q1 c180 Q0 c90 c270 DV T0 T1 Trans. Detection & Encode 4Ch Coarse Time Counter TS Logic elements with non-critical timing are freely placed by the fitter of the compiler. This picture represents a placement in Cyclone FPGA Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  31. A 96 Channel TDC Module 48CH TDC FPGA 48CH TDC FPGA Data Concentration FPGA Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  32. The 96 CH TDC Module Specifications Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  33. Some Important Details on Coarse Time Counters • Connecting coarse time with the fine time is normally considered a “challenge”. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  34. Issues of Coarse Time Counter 000 001 011 010 110 111 101 100 Coarse Time Counter Coarse Time Counter Gray Code Counter Coarse Time Counter • There are some common misunderstandings on coarse time counters in a TDC: • Tow coarse time counters are needed, driven by clocks with 180 degree phase difference. • The coarse time counter should be a Gray code counter. • Actually, dual counters and/or Gray code counters are only needed in one ASIC TDC architecture. • In the architectures used by FPGA TDC and some ASIC TDC, only one plain binary counter is needed as coarse time counter. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  35. HIT HIT HIT CLK CLK CLK CLK HIT Delay Line Based TDC Architectures Only this architecture needs dual coarse time counters. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  36. Implementation of Coarse Time Counter Coarse Time Counter Coarse Time In Fine Time Encoder Fine Time ENA CLK Hit Detect Logic Data Ready Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  37. Differential Inputs and Multiple Thresholds • An FPGA can handle many differential inputs and each input can feed a TDC functional block. • Multi-threshold approach is commonly used to compensate time-walk due to amplitude variation. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  38. T3 T1 T0 2Vth 8Vth T2 T4 Differential Dual Threshold for PMT T0 = (T1+T2)/2 – ((T3+T4)/2-(T1+T2)/2)/4 T3 • Four comparators: two for +- signals, two for signals vs. fix thresholds. • Insensitive to amplitude, threshold voltage, common mode noise. • High resolution TDC is needed only for T1 and T2, not T3 and T4. T1 T2 T4 Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  39. Insensitivity to Common Mode Level T3 T0 T1 8Vth 2Vth T2 T4 T0 = (T1+T2)/2 – ((T3+T4)/2-(T1+T2)/2)/4 • Typically, differential noise << common mode noise. • The common mode level variation is canceled in (T3+T4). • Large common mode noise is tolerated. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  40. Another Differential Dual Threshold Input Circuit T1 T3 T0 8Vth T2 T3 T1 T2 Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  41. Summary • FPGA TDC covers wide range of applications: • TOF, Delta T RMS resolution: 20-25ps: Delay Line. • Drift Chamber, LSB 0.5-1ns: Multi-sampling. • After-fact digital calibration instead of analog compensation is more convenient for FPGA TDC. • Multiple-measurement method is used in the Wave Union TDC to improve performance. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  42. The End Thanks Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  43. TDC Back End Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  44. Calibration Resource Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  45. Timing Diagram Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  46. “Wavelet TDC” --> “Wave Union TDC” • This design was named “Wavelet TDC”. • Criticism was received for confusion that may be caused by using “Wavelet”. • It is now renamed as “wave union” TDC. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  47. Wave Union Launcher B: Delta T • Plain TDC: • delta t RMS width: 40 ps. • 25 ps single hit. • Wave Union TDC B: • delta t RMS width: 12 ps. • 8 ps single hit. Wave Union TDC B (+) Random Input Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  48. FPGA and ASIC • FPGA is not the best vehicle to pursue the resolution frontier. (Double-digit ps). • However, some tricks can be cross-transplanted between FPGA & ASIC: • Multi-measurement method. • Auto calibration to eliminate PLL and to tolerate DNL as silicon process goes finer. Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  49. Auto Calibration Delay Line in ASIC TDC DF Encoder Wu, Jinyuan (jywu168@fnal.gov) Fermilab

  50. The End Thanks Wu, Jinyuan (jywu168@fnal.gov) Fermilab

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