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High resolution TDC based on FPGA for TOF measurement. Ji Qi with Yinong Liu, Zhi Deng, Yi Wang Tsinghua University. Outline. FPGA TDC Design Test results TDC electronics TOF spectrum with MRPC Summary and future plan. FPGA TDC: prons and cons. Advantages
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High resolution TDC based on FPGA for TOF measurement Ji Qi with Yinong Liu, Zhi Deng, Yi Wang Tsinghua University
Outline • FPGA TDC Design • Test results • TDC electronics • TOF spectrum with MRPC • Summary and future plan
FPGA TDC: prons and cons • Advantages • High integration and flexibility, SOC • Short period of development • Low cost • Disadvantages • Tempurature dependent • Poor linearity control
The time intepoltaion methods Vernier caliper method Delay chain method S.S. Junnarkar, P O'Connor et al., IEEE Nuclear Science Symposium Conference Record, 2008 J. Wu and Z. Shi, IEEE Nuclear Science Symposium Conference Record, 2008
Implementation • Delay chain Signal in Signal out tap tap tap tap clk tap tap tap tap tap tap Signal in Signal out
Real time calibration Bin width [ps] Bin code RMS of a bin width [ps] Total number of calibration hits
DNL Linearity Performance INL
Timing Resolution rms=38.7ps two channels rms=27.4psone channel for bin width <50 ps
Preliminary Spectrum Test Count [cnts/ps] Time residual [ps]
Test with MRPC Detector Fast Scintillator and PMT FPGA TDC MRPC and its frontend board NIM to TTL
Preliminary TOF Spectrum Total count = 6390
Summary and Future Plan • An FPGA TDC using delay chain has been developed and tested. It achieve 27ps rms resolution for more than 84% bins. • The temperature shift is measured to be up to 100ps from 10 degree to 40 degree. So it needs temperature control before we find the source. • A newer frontend ASIC with TOT information will be developed in the near future and then we can do the TOF measurement with MRPC detectors more precisely.