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FutureDAQ Kick-off

FutureDAQ Kick-off. Network Design Space Exploration and Analysis Computer Architecture Group Prof. Brüning. Patrick R. Haspel haspel@uni-mannheim.de Computer Architecture Group University of Mannheim, Germany. Research & Projects. Actual projects ATOLL: Networkinterface for SANs

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FutureDAQ Kick-off

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  1. FutureDAQ Kick-off Network Design Space Exploration and Analysis Computer Architecture Group Prof. Brüning Patrick R. Haspel haspel@uni-mannheim.de Computer Architecture Group University of Mannheim, Germany

  2. Research & Projects • Actual projects • ATOLL: Networkinterface for SANs • OASE: Optical Datatransmission • Research Areas (Computer Architecture) • Parallel- and Cluster computing using innovative Computer Architectures • low latency Interconnection Networks • high performance chip design using leading edge EDA Tools (proven cell based design flow) • Research Areas • (Optoelectronics, Prof. Brenner) • Microoptical System Interconnects for digital communication (board to board, chip to chip) • 3D Microintegration of optical components • Actual projects • OASE: Optical Data Transmission • Blue DVD lens for Laser beam shaping • Microoptical components fabrication

  3. ATOLL – System Area Interconnect • ATOLL • Extreme low-latency network (currently fastest worldwide) • Distributed switching resource (X-Bar) -> massively scalable • Arbitrary network topology

  4. ATOLL2d Torus Topology Example Node with an ATOLL NIC All topologies fitting to the 4 interconnects are supported ...

  5. NIC NIC NIC ATOLLTree Topology Example

  6. ATOLL-ASICBasic Architecture Reliable links 2 GByte Bisection bandwidth ~80ns 4,5 Mio transistors Cell based design (>1 Mio gates) 0.18µm CMOS process 5,7 x 5,7 mm Chip Fastest and Second Biggest Chip Design of a European University

  7. Optimization for Performance and Cost

  8. OASE Architecture • OASE integrated optical interconnect (1x, 4x, 8x, Nx) Patent pending

  9. Custom Network @ CBM • Advantages of a customized interconnection network – Using full network design space by: • Network tuning – Application optimized network parameter (Latency/Bandwidth/Topology) • Adopting network interface to simplify front-end electronic (physical/protocol level) • Expanding network function (data transport -> data manipulation) • Introducing computing in the network (CPU on network interface)

  10. Customization process • System level evaluation and simulation (architecture and behaviour level) • SystemC – development suite using C/C++/SystemC based models • Building Block Modelling • Message Passing protocol specification - Transport Packet Design • Networkanalysis and Interfacedesign • platform development for software development (HW/SW cosimulation) • optional CoWare simulation and analysis environment for advanced debugging

  11. Proposal for CBM • Let the network sort your packets • Let the network manage load balancing • Regarding node utilization (automatic target selection) • Regarding network congestion (dynamic routing) • Use programmable packet engine on the network interface to do arbitrary data manipulations • Computing in the network (data is manipulated travelling through the network)

  12. Thank you!

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