Design and Implementation of VLSI Systems (EN0160) Lecture 29: Datapath Subsystems 3/3

1. Design and Implementation of VLSI Systems (EN0160) Lecture 29: Datapath Subsystems 3/3 Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Last two lectures We talked about different kind of adders This lecture Comparators Shifters Multipliers Outline

3. 0’s detector: A = 00…000 1’s detector: A = 11…111 Equality comparator: A = B Magnitude comparator: A < B Comparators

4. 1’s detector: N-input AND gate 0’s detector: NOTs + 1’s detector (N-input NOR) When is this circuit structure a good idea? 1. 1’s and 0’s detectors

5. Check if each bit is equal (XNOR, aka equality gate) 1’s detect on bitwise equality 1. Equality comparator

6. 1. Magnitude comparator • Compute B-A and look at sign • B-A = B + ~A + 1 • For unsigned numbers, carry out is sign bit

7. Shifting a data word by a constant amount is trivial A programmable shifter is more complex 2. Shifters Multibit shifter can be cascaded together

8. 2. Barrel Shifter • Signal passes through at most one transmission gate • Total transistors = N2 • Dominated by wiring

9. 2. Logarithmic shifter • Total shift is decomposed into stages of 2 • Speed of shifting N bits depends on log N • Number of transistor = 2(log N)* N

10. Multipliers

11. Array multiplier Where is the critical path?

12. Critical path of MxN multiplier

13. Carry Save Multiplier The carry bits are not immediately added, but rather are “saved” for the next adder stage