Design and Implementation of VLSI Systems (EN0160) Lecture 25: Sequential Circuit Design (3/3)

1. Design and Implementation of VLSI Systems (EN0160) Lecture 25: Sequential Circuit Design (3/3) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Time Borrowing • In a flop-based system: • Data launches on one rising edge • Must setup before next rising edge • If it arrives late, system fails • If it arrives early, time is wasted • Flops have hard edges • In a latch-based system • Data can pass through latch while transparent • Long cycle of logic can borrow time into next • As long as each loop completes in one cycle

3. We talked about two things: Maximum propagation delay and relationship with clock period and setup time Minimum (contamination) delay and relationship with hold time Last lecture

4. Time borrowing illustrated

5. How much can we borrow? 2-Phase Latches Pulsed Latches

6. We have assumed zero clock skew Clocks really have uncertainty in arrival time Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing Clock Skew

7. Skew: flip-flops

8. Skew: 2-phase latches

9. FFi FFj FFk Skew is not always bad! (Useful Skew) dmax =8ns dmax =10ns si sj • Zero clock skew (si =0 & sj = 0)  clock period = 10ns, fmax = 100MHz • Si = 0 sj = 1ns  clock period = 9ns, fmax = 111MHz (no timing violations) • Si = 0 sj = 2ns  clock period = 8ns, fmax = 125MHz (no timing violations) • Introducing skew also helps minimize the simultaneous switching of FFs  less load on the P/G network

10. 7.1/7.2/7.3 HW5: Exercises: 7.2, 7.4, 7.6, 7.10 Due Date: Wed 11th of April We are done with the main sections of chapter 7

11. Entire class will collaborate on designing a simple MIPS CPU I will go through the CPU description next time in class Today, we can get a head start by working on designing the standard cell library Project

12. Main standard cells: Inverter (done) Tri-state buffer 2-input and 3-input NAND 2-input and 3-input NOR 2-input XOR 2x1 MUX Latch/FlipFlop AOI Expected height 70λ (give or take ) Standard cell design

13. I will distribute the template library as well as the clean 0.5AMI Tanner technology files. Each person required to design a cell. On Monday April 9 before class, deliver your cells to the library Integrator, together with half a page of text that describes: Cell layout Functional verification diagrams from SPICE simulations Delay and power estimates, Library Integrator will make copy all cells into the same library file (make sure they all comply with standard) and create one text file from all input descriptions. Integrator will iterate with any persons that have design problems. Deadline for library integrator is Wed April 11. Required tasks

14. Cell Design Methodology • New library has slightly different rules than before • I designed an inverter as a guideline • Let’s have power lines on metal 1 horizontally and input/output lines vertically on metal 2