Power estimation

1. Power estimation • General power dissipation in CMOS • High-level power estimation metrics • Power estimation of the HW part • Power estimation of the SW part • Simulations and results • Source: • W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano • “Power Estimation of Embedded Systems….” • IEEE Transactions on VLSI systems, V6, N2, 1998 Mehdi Amirijoo

2. General power ... • Estimating from system-level point of view. • Average power is related to the switching activity of the circuit nodes. • Power dissipation in CMOS devices is composed of a static and a dynamic part. Dynamic part is the most dominant. • CEFF is the effective switched capacitance. Mehdi Amirijoo

3. General power ... • i is the switching activity factor at node i. We assume spatial and temporal independence between nodes. • Also define the toggle rate as: Mehdi Amirijoo

4. High-level power estimation • The power dissipation in timing-constrained systems depends on the mode of computation: • Fixed throughput • Maximum throughput • Burst throughput • Metric for Fixed throughput: • Metric for Maximum throughput: Mehdi Amirijoo

5. High-level power estimation • For an area-constrained system the following metric is efficient: • Metric for Burst throughput: • Systems with power shutdown techniques, ETR else MBurst Mehdi Amirijoo

6. Power Estimation of HW part • Analytical model based on VHDL description at behavioral/RT level and the probabilistic estimation of the internal switching activity. • Hierarchical estimation approach. • User supplied input probabilities rather than input patterns. • Assumptions: • The supply and ground voltage are fixed. • Synchronous sequential circuits. • Data transfer at register-register level. • ZDM Mehdi Amirijoo

7. Power Estimation of HW part • Inputs to the estimation: • The ASIC spec. • The allocation library, components implementing the macro-modules and the basic modules. • The technological parameters. • The switching activity of the I/O’s • The total average power dissipation is given by: • Average power dissipated by the I/O nets • Core internal nets Mehdi Amirijoo

8. Power Estimation of HW part • For estimating the PIO factor requires knowledge about switching activity (given by the spec) and the pad characteristics (capacitance etc). • PDP is divided into the following: • Data-path PDP , memory PMEM , control logic PCNTR , core processor PPROC Mehdi Amirijoo

9. Power Estimation of HW part • PMEM is proportional to: and We assume to have Pi,m in the target library Mehdi Amirijoo

10. Power Estimation of HW part • Model the control unit as a probabilistic FSM - Markov chain. • The input signal probabilities (input switching activity factors) are obtained from the system-level specification. Also assume ZDM. • The average power dissipated by the kth input, depends on the switching activity factor k and the input load capacitance Ck • P can be divided into: Mehdi Amirijoo

11. Power Estimation of HW part • Let pij = P(next = sj | present = si), conditional state transition probability. • Let Pi be the steady state probability of the state si(the probability to be in a certain state in an arbitrarily long sequence. Given the Markov chain we can solve this problem by solving the Chapman-Kolmogorov equations). • Let Pij = pijPi be the total state transition probability. • Px(Cx) is the average power consumption per MHz. Mehdi Amirijoo

12. Power Estimation of HW part • TP, transition probability between two disjoint subsets • S = {s1, s2, …. , sn} • Si and Sj are disjoint subsets of S • Power dissipation of register (in general) can be divided into a switching and non-switching power. Mehdi Amirijoo

13. Power Estimation of HW part • Switching power Pi relates to the toggle rate TRbi of the output of the register, while the PNSi relates to the power consumption during the clock edges. • Pi (or TRbi)depends on the state switching activity and the state encoding. • bi is the ith bit of the state code (state bit). Mehdi Amirijoo

14. Power Estimation of HW part • Estimation of PCOMB • Assume a gate X. • Ci is the capacitance driven by the ith gate X. • Pi(Ci) is the average power consumption per MHZ of the ith gate X. • TRi is toggle rate of the gate X (based on the probabilistic model of switching activity of X). Mehdi Amirijoo

15. Power Estimation of HW part • Moore-type FSM, • Power dissipation of POUT is composed of a part related to the combinatorial net and a part related to the primary outputs driving the output capacitance. • The total state transition probabilities Pij between two states si and sj are equal to the total transition probabilities between the corresponding outputs oi and oi Mehdi Amirijoo

16. Power Estimation of SW part • Bottom-up approach (TOSCA). • In TOSCA the specification is compiled in the VIS, by considering the average power consumption of each VIS instruction during the execution of a given program. Choosing VIS-level makes the analysis processor independent. • Estimate the power consumption of each block. • Estimate the total power consumption by weighing the power consumption of each block according to execution frequencies. Mehdi Amirijoo

17. Power Estimation of SW part • The average current or energy (VDD is fixed) of each instruction can be derived by: • Measurements or detailed information from the provider • However we have overheads in forms of pipeline stalls, cache misses etc. • The overheads have been measure to be less than 5% of the base energy per instruction. • Add the overheads to the base energy cost. • In general… Mehdi Amirijoo

18. Simulations and results • Background: • 35 FSM’s from the MCNC-91 benchmark suite. • HCMOS6 tech, 0.35 um, 3.3 V, 100 MHz • FSM’s synthesized by Synopsys Design Compiler • Comparing to Sysnopsys Design Power (based on the synthesized gate-level netlist). • Average percentage error of 9.52% (0.01-25.8%) Mehdi Amirijoo

19. Simulations and results Mehdi Amirijoo