Power Estimation of Digital Systems

1. SatyaKiran Power Estimation of Digital Systems 22 September 2003

2. Introduction • Why power of nano-electronics became so important? • Because of Moore’s law still holds true through complex applications • Mobile systems – battery “bottleneck” • High performance computation – heat extraction • Operating cost and reliability • Data warehouse of ISP with 8000 servers needs 2 MW • Power or Energy? Aren’t they go hand-in-hand? • Power varies significantly with time! • A given battery has fixed amount of energy • Average power consumption = Energy/Execution-time • Decides average chip and junction temperature • Decides battery life (if peak current < rated current) • Peak power and current • Voltage drops, hot spots, rate of battery discharge • Power-efficient, Energy-efficient, Battery-efficient design paradigms do exist!

3. Components of Power Consumption • System = hardware platform + software (sys. & app.) • Software impacts hardware power consumption • Static power • Sub-threshold leakage & reverse biased junction leakage • Quiescent biasing power (in case of non-CMOS circuits) • Dynamic power • Charging and discharging of capacitance (switching activity) • Short circuit power during transition (rate of change, delay) • Alternative grouping (used at component/cell level) • Switching power at the boundaries of cells • Internal cell power • Short circuit power • Switching power at internal nodes

4. System Abstractions - Power Functional Specifications and Constraints System Level Netlist Register Transfer Level (RTL) Netlist Component/Cell Level Netlist Layout or Configuration-bits Chip Time complexity Accuracy of power characterization Opportunities for optimization

5. Power Characterization • Measurement (Chip/Board Level) • Most accurate • Perhaps the fastest, if setup and tools exist • Too late to change hardware details • Software/Load control is still possible • Typically used for software optimizations • Transistor Level (estimation) • Spice simulation of transistor level netlist • Most accurate in the simulation world • Requires complete implementation details • Unmanageable time complexity even for simpler designs • Typically used for cell/component characterization • Synopsys PowerMill (said to provide spice-like accuracy)

6. Power Characterization (cont…) • Cell Level (estimation) • After logic synthesis • Requires RTL implementation • Simulation to capture switching activity • Requires delay simulation if glitches need to be accounted • Characterized cells – empirical formulas or table look-up • Interconnect power • Either unaccounted or • Using estimated wire load models (typically based on experience) or • Extracted layout (if done after physical synthesis) • Still unmanageable time complexity especially to use in design space exploration • Synopsys PrimePower • Netlist, interconnect capacitance, VCD traces, cell power library

7. Power Characterization (cont…) • Register Transfer Level (estimation) • Requires conceptual RTL description (detailed micro-architecture) • Data-path is modeled as netlist of macro cells, which are characterized offline • Control path and glue logic • Either unaccounted or estimated based on I/O • Simulation to capture switching activity • Typically glitches are not considered but methods do exist • Interconnect power • Typically unaccounted but possible to estimate through floor-planning • Typically used in DSE mostly using in-house tools • Synopsys PrimeCompiler – but too naive • Synthesizable RTL, switching activity, power library

8. System Level Power Estimation • For Design Space Exploration • Least accurate but uncertainty of exploration results can be reduced if models have good fidelity • Purpose, target architecture and available system details govern the system-level estimation models • Selecting algorithm or designing hardware for given algorithm? • ASIC based or processor based? • Is ISA fixed or extensible? • Typically system-level power estimation models are macro-architecture template specific • Major constituents of power consumption • Computation, communication, storage units & peripherals

9. Power Estimation Models • Instruction Level Power Estimation • First introduced to characterize processor power consumption to drive software optimizations • Each instruction is associated with some current • Inter instruction effects for better accuracy • Later experiments on StrongARM by Amit Sinha & APC • Current/instruction ~ 0.2A (averaged over all instructions) • Min-max variation of 38% of average current • Address mode and data dependent variation is smaller • But, max current variation across benchmarks is < 8% ! • Concluded that first order energy model of a given processor is, E = V I(V, f) T • Second order effects can be significant for data-path dominated processors such as DSP, VLIW

10. Power Estimation Models (cont…) • Second order effects are best characterized by events which can be obtained from simulation • I = ( W1 C1 + W2 C2 + … ) I0(V, f) • C denotes event frequency • W denotes associated weight (obtained by characterization) • Events can be either fine-grained or coarse grained • Events can be classes of instructions or • Micro-architecture component/sub-component accesses (WATTCH) or • Events such as normal accesses, stalls, … • Power State Machines by Luca Benini et. al. • States of the FSM represent mode of operation • Active, Idle, Power off, … • Transitions are labeled with triggering events, transition energy cost and perhaps transition times • Abstract specification to generate events can be accompanied • Useful to analyze power management schemes

11. Power Estimation Models (cont…) • Integration of both the above models results in a more powerful model • States of the FSM represent mode of operation • Certain events cause state change and certain don’t • Power/energy consumption in each state can be event and parameter dependent (empirical formulas, table look-ups) • Read and write access of memory in active mode • ADD and MUL instructions of a processor • # of transitions of a bus • Transitions are labeled with triggering events, transition energy cost and perhaps transition times • Abstract specification to generate events can be accompanied • Useful for both system-level and RTL power estimation of wide variety of components • Trade-off of accuracy Vs characterization effort is possible

12. Questions?