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Analog Front End for the fiber tracker in Dzero

Learn about the detailed functions and design of the Analog Front End (AFE) for the fiber tracker in DZero by D. Smirnov, including its importance, operation, and key features. Explore the board layout, chip testing, installation, and project management aspects. Gain insights into the lessons learned through the development process.

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Analog Front End for the fiber tracker in Dzero

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  1. Analog Front End for the fiber tracker in Dzero for D Smirnov

  2. AFEII-t Outline • What • How • Why • Lessonslearned for D Smirnov

  3. VLPC VisibleLightPhotonCounter • very high QE • good gain • low noise makes fiber tracker possible! no light a little light for D Smirnov

  4. Analog Front End(AFE) VLPC ~8 photons from fiber VLPC 9o K ~50 fC to AFE 200 brds ~ 100K ch total in Dzero CFT cylinder DISCR Discriminator output every 396 nsec for L1 Amplitude signal readout for L3 and offline ADC AFE (512 ch) for D Smirnov

  5. Analog Front End (AFE) 3 main responsibilities • Care and feeding of the VLPCs (via slow control) • Bias (±40mV) • Temperature control (±0.05K) • Hit/no hit decision to the trigger system every crossing, every fiber. • Used in forming Level 1 decision • 512 ch/board, every BX ( max 485 MB/s) • Amplify VLPC signals, digitize to 8 bits, zero suppress and readout every on L1 accept • max 40 MB/s • Readout via same system as silicon strip vertex detector for D Smirnov

  6. TriP-t • AFE is designed around the TriP-t • Trigger and Pipeline – with timing • 32ch/chip: discr,48 cell analog pipeline ea. • 0.25um CMOS manufactured by TSMC • TriP-t ASIC designed specifically for Dzero VLPC based detectors: CFT, CPS, FPS • TriP-t designed by Fermilab ASIC group, A. Mekkaoui lead designer • Fermilab has a strong ASIC group, lots of experience, wide range of capabilities • slow control from FPIX, pipeline from SVX4 for D Smirnov

  7. TriP-t Block Diagram • TriP-t R Yarema, 2005 for D Smirnov

  8. TriP-t • TriP-t • Q sense front end : DC stable wide dynamic range high bandwidth low noise Very flexible: adjustible gain adjustible bandwidth for D Smirnov

  9. TriP-t • Some parameters • integration gate: 50ns to 20us, controlled by external clock • gain: 12mv/fC to 0.37mv/fC, switch set • pipeline depth 1 to 47, dead-timeless • noise: ~1fC for 40pF input capacitance • low power: 6.5mW/ch • discriminator thresh: 1/chip, 10fC to 300 fC • TDC: 1ns resolution for more info: rubinov@fnal.gov for D Smirnov

  10. AFE and TriP-t design TriP-t ideas: • “keep it simple” do only what can not be done with commercial ICs ADC is external, zero suppression in external FPGA • “keep it flexible” internal DACs (set via serial interface) can be used to adjust bandwidth, power, gain flexible clocking scheme, driven by FPGA • “ease of use” temperature compensated to first order features to support testing, calibration for D Smirnov

  11. AFE board design to CTT system • Modular design • Xilinx Spartan2 FPGA to handle discr data • Xilinx Spartan2 FPGA to handle analog data • FPGAs format data • AFPGA used tozs and ped sub • Every module has its own LDOs • FPGAs have identf/w- can downloadvia slow control DiscrFPGA RO chain to L3 AnalogFPGA AnalogFPGA ADC ADC ADC ADC TRIP TRIP TRIP TRIP for D Smirnov

  12. AFE and TriP-t design Board ideas: • Better performance is achieved not when new boards are designed and built, but only when the are installed, calibrated, integrated with all software layers. So do everything to make it easy to “plug and play” • Design for manufacturing, design for test, worry about how you are going to debug and fix the boards for D Smirnov

  13. Lessons learned • dumbest things we did on the AFEII • we have a sporadic issue with crosstalk between the discriminators and the temperature control: to limit self heating in the carbon resistor, temperature sensing is done with a 10uA current- and we must be sensitive to changes of less than 1 ohm. So large gain is required. We worried about this, but did not do sufficient testing in “worst case” conditions. Smart thing would have been to time the temp sensing only when there is no activity- such as during a beam gap. temp control follows luminosity on 5% of boards for D Smirnov

  14. Lessons learned • Crosstalk between A output and t output • Reduces signal gain relative to TAC output off by 7% • Hurts timing resolution A out t out 1mm TAC disabled TAC enabled for D Smirnov

  15. Conclusions • AFEII is a success for Dzero • mostly because TriP-t is briliant • No ASIC is perfect- every one has its quirks • get the simplest ASIC that will do the job • but no simpler! for D Smirnov

  16. SPARE SLIDES AFTER THIS POINT

  17. Who Problem statement and proposals B. Hoeneisen, J. Estrada, M. Johnson, F. Borcherding,M. Hildreth, C. Garcia, S. Gruenedahl Chip design A. Mekkaoui, T. Zimmerman, J. Hoff Engineering J. Anderson, S. Rapisarda, T. Fitzpatrick, K. Bowie,R. Angstadt Board layout and production N. Moibenko, T.Wesson, J.Green, B.Merkel Chip testing L.Bellantoni, A.Baumbaugh, K.Knickerbocker, R.Klien, C.Gingu for D Smirnov

  18. Who Board testing V. Yakimchuk, M. Kostin, B. Freemire, M. Wojcik, K. Kuk,P. Liston, J. Osta, S. Schlobohm, T. Dorland Installation and operations J. Warchol, G. Ginther, D. Smirnov, N. Khalatyan,J. Degenheart Project management V. Odell, B. DeMaat, A. Bross, J. Blazey, J. Kotcher CPS D. Alton, A. Evdokimov, A. Patwa for D Smirnov

  19. Who for D Smirnov

  20. AFE 1 and AFE 2 have the same analog gain Run 216593 (AFE1), 216622(AFE2) AFE 1 AFE 2 for D Smirnov

  21. AFEII, CFT axialdiscriminator off, discriminator on Run 216928,216934 for D Smirnov

  22. New firmware, board 13A4, SVX2, TriP #1 for D Smirnov

  23. 8B7, 8B1, Temperature in Cassettes vs Time 8B7 Installation of AFEII boards, 1-Nov. 8B1 for D Smirnov

  24. 8B7, 8B1, 13-Nov to 16-Nov • 15 Nov 06 • Re-inserted bayonet in 8B1, • Swapped out 8B7 (221 in) 8B7, swapped AFEII board 8B1, re-inserted bayonet for D Smirnov

  25. 8B7, 8B1 24-Nov. to 4-Dec 06 • 8B7 starts developing some spikes, but for now, at low level • 8B1 developed spikes some time after bayonet re-insertion on 15 Nov 06, bayonet got re-inserted again on 26Nov 06 8B7 26 Nov, bayonet again re-inserted in 8B1 8B1 for D Smirnov

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