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Conceptual LLRF design for 1.3GHz superconducting cavity

Conceptual LLRF design for 1.3GHz superconducting cavity. Qiu Feng ( PH.D Student ) LLRF members : Wang Guang wei, Sun YI Liu Rong, Zeng Ri hua, Qiu Feng Lin Hai ying, Wang Qun yao Mini-workshop of 1.3GHz/9cell superconducting cavity IHEP Dec. 2 2009. Content.

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Conceptual LLRF design for 1.3GHz superconducting cavity

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  1. Conceptual LLRF design for1.3GHz superconducting cavity Qiu Feng ( PH.D Student ) LLRF members : Wang Guang wei, Sun YI Liu Rong, Zeng Ri hua, Qiu Feng Lin Hai ying, Wang Qun yao Mini-workshop of 1.3GHz/9cell superconducting cavity IHEP Dec. 2 2009

  2. Content • 1. Target and the whole Block Diagram • 2. Signal and Clock • 3. RF Down-Conversion and Up-Conversion • 4. Algorithm

  3. 1. Target and the whole Block Diagram • 1. Requirements on field stability (approximately RMS requirements) 0.1% for Amplitude and 0.1° for Phase • 2. Chain secure • 3. Take fully advantages of DSP technology

  4. 1. Target and the whole Block Diagram

  5. 2. Signal and Clock • 1. Super-Sampling • LO: 1301MHz • Sampling Clock: 100MHz • 2. RF signal and Sampling Clock • RF signal source: 8663A • (0.1MHz~2560MHz). • Sampling Clock: 33220A • Reference signal : 10MHz

  6. 1401Mhz 1300Mhz DBM DBM 1301Mhz 1300Mhz 100Mhz 101Mhz 2. Signal and Clock • How to generate the Local Frequency? • The AD9858 can generate the 101MHz signal with its Clock(1300MHz RF signal). • After twice frequency Mixing, we can get the 1301MHz Local signal, then we can obtain the 1MHz IF signal by mixing the RF and LO.

  7. 2. Signal and Clock The overall diagram of Clock structure

  8. 3. RF down conversion and up conversion • Analog down conversion

  9. 3. RF receiver • Analog up conversion

  10. 4. Algorithm • Digital down conversion • How to generate IQ? • Scheme1(experienced)

  11. 4. Algorithm • Feedback Algorithm

  12. 4. Algorithm Simulink of 500MHz experiment

  13. 4. Algorithm • Feedforward Compensation • The feed forward can supplement the feedback. it can suppress the known repetitive error.

  14. 4. Algorithm • Digital up Conversion • Scheme1(experienced)

  15. 4. Algorithm • Digital up Conversion • Scheme2

  16. 4. Algorithm • Tuner control The cause of de-tuning

  17. 4. Algorithm • Tuner control • For CW working mode，the diagram above is appropriate，for pulse working mode, the table test need to be done in the near future.

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