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MCF5249 Software Examples Bootable example code for the MCF5249

MCF5249 Software Examples Bootable example code for the MCF5249. Init. FAT. Simple. Software Examples Overview. Init Module. Processor and on-chip peripheral initialization Building block for all other modules. Init. FAT. Simple. Processor Initialization. Reset Signal (RSTI).

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MCF5249 Software Examples Bootable example code for the MCF5249

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  1. MCF5249 Software ExamplesBootable example code for the MCF5249

  2. Init FAT Simple Software Examples Overview

  3. Init Module Processor and on-chip peripheral initialization Building block for all other modules Init FAT Simple

  4. Processor Initialization Reset Signal (RSTI) VBR initialized to 0x0000_0000 ChipSelects reset CS0 is active *See Section 3.5.12 of MCF5249 User’s Manual SP and PC fetched from Vector Table in vectors.s Provided in ‘init’ module Low-level processor initialization in mcf5249_lo.s On-chip peripheral initialization in sysinit.c Main Process

  5. Reset Exception • Processor is placed in the supervisor mode • VBR is initialized to 0x00000000 • The first entry in the vector table (0x0) is loaded into the stack pointer (SP) • The second entry in the vector table (0x4) is loaded into the program counter (PC) • After the initial instruction is fetched from memory, program execution begins at the address in the PC vectors.s : • Contains complete exception vector table including initial SP and PC

  6. vectors.s • /* Exception Vector Table */ • VECTOR_TABLE: • INITSP: .long ___SP_INIT /* Initial SP */ • INITPC: .long 0x400 /* Initial PC */ • vector02: .long _asm_exception_handler /* Access Error */ • vector03: .long _asm_exception_handler /* Address Error */ • vector04: .long _asm_exception_handler /* Illegal Instruction */ • vector05: .long _asm_exception_handler /* Reserved */ • vector06: .long _asm_exception_handler /* Reserved */ • vector07: .long _asm_exception_handler /* Reserved */ • vector08: .long _asm_exception_handler /* Privilege Violation */ • vector09: .long _asm_exception_handler /* Trace */ • vector0A: .long _asm_exception_handler /* Unimplemented A-Line */ • vector0B: .long _asm_exception_handler /* Unimplemented F-Line */ • vector0C: .long _asm_exception_handler /* Debug Interrupt */ • vector0D: .long _asm_exception_handler /* Reserved */ • vector0E: .long _asm_exception_handler /* Format Error */ • vector0F: .long _asm_exception_handler /* Unitialized Int. */ • vector10: .long _asm_exception_handler /* Reserved */ • vector11: .long _asm_exception_handler /* Reserved */ • vector12: .long _asm_exception_handler /* Reserved */ • vector13: .long _asm_exception_handler /* Reserved */ • vector14: .long _asm_exception_handler /* Reserved */ • vector15: .long _asm_exception_handler /* Reserved */

  7. Low-level Initialization mcf5249_lo.s : • Initializes internal SRAM • Initializes MBAR - pointer to on-chip module memory map • Sets up temporary stack in internal SRAM • Calls higher level module initialization • Provides low-level routines to manage cache • Provides functions for writing internal control registers

  8. mcf5249_lo.s • /* This is the main entry point upon hard reset. */ • asm_startmeup: • /* Invalidate the cache and disable it */ • move.l #0x01000000,d0 • movec d0,cacr • /* Initialize SRAMBAR: locate SRAM and validate it */ • move.l #0xE0000021,d0 • movec d0,RAMBAR • /* Point SP into SRAM (temporarily). SRAM is used as stack space • * while initializing the mcf5249 periphs and memory controller. */ • move.l #0xE0000000+SRAMsize,SP • .... • /* Initialize mcf5249 periphs, etc */ • move.l d6,-(sp) /* pointer to internal resources */ • jsr mcf5249_init • lea 4(sp),sp • .... • jmp main • /******************************************************************** • * These routines write to the special purpose registers in the ColdFire • * core. Since these registers are write-only in the supervisor model, • * no corresponding read routines exist. • */ • mcf5249_wr_vbr: • _mcf5249_wr_vbr: • move.l 4(sp),d0 • andi.l #0xFFF00000,d0 /* align to 1M boundary */ • movec d0,VBR • nop • rts • mcf5249_wr_cacr: • _mcf5249_wr_cacr: • move.l 4(sp),d0 • movec d0,cacr • nop • rts • mcf5249_wr_acr0: • _mcf5249_wr_acr0: • move.l 4(sp),d0 • movec d0,ACR0 • nop • rts • /******************************************************************** • * mcf5249 has Icache only • */ • cpu_cache_flush: • _cpu_cache_flush: • nop /* sync */ • move.l #0x01000000,d0 /* Invalidate the I-Cache */ • movec d0,cacr • rts • /******************************************************************** • /* • * This routine is the lowest-level exception handler. • */ • asm_exception_handler: • _asm_exception_handler: • move.l (sp),a1 • move.l a1,-(sp) • jsr exception_handler • lea 4(sp),sp • rte

  9. On-chip Peripheral Initialization sysinit.c : • Initializes SDRAM • Copies variable data from non-volatile memory to SDRAM • Initializes UARTs for I/O • Initializes the SIM and Chip Select modules appropriately for the M5249C3 evaluation board

  10. sysint.c • /* • * Out of reset, the low-level assembly code calls this routine to • * initialize the MCF5249 for this board. A temporary stack has been • * setup in the internal SRAM, and the stack pointer will be changed • * to point to SDRAM once this routine returns. • */ • void • mcf5249_init (MCF5249_IMM *imm) • { • mcf5249_uart_init(imm); • mcf5249_sim_init(imm); • mcf5249_gpio_init(imm); • mcf5249_cs_init(imm); • /* Turn Instruction Cache ON */ • mcf5249_wr_cacr(0x81000500); • /* Copy the vector table to RAM */ • if (__VECTOR_RAM != VECTOR_TABLE) • { • for (n = 0; n < 256; n++) • __VECTOR_RAM[n] = VECTOR_TABLE[n]; • } • mcf5249_wr_vbr((uint32)__VECTOR_RAM); • /* Move initialized data from ROM to RAM. */ • if (__DATA_ROM != __DATA_RAM) • { • dp = (uint8 *)__DATA_RAM; • sp = (uint8 *)__DATA_ROM; • n = __DATA_END - __DATA_RAM; • while (n--) • *dp++ = *sp++; • } • /* Zero uninitialized data */ • if (__BSS_START != __BSS_END) • { • sp = (uint8 *)__BSS_START; • n = __BSS_END - __BSS_START; • while (n--) • *sp++ = 0; • }

  11. Processor Definition File mcf5249.h : • #define for all internal memory-mapped registers • read/write access macros for all internal registers • bit level definitions and macros

  12. mcf5249.h /********************************************************************** * SDRAM Controller Module Registers Description ***********************************************************************/ /* Offsets of the registers from the MBAR */ #define MCF5249_SDRAMC_SDCCR (0x0180) #define MCF5249_SDRAMC_SDCTR (0x0184) /* Read access macros for general use */ #define MCF5249_RD_SDRAMC_SDCCR(IMMP) \ Mcf5249_iord(IMMP,MCF5249_SDRAMC_SDCCR,32) #define MCF5249_RD_SDRAMC_SDCTR(IMMP) \ Mcf5249_iord(IMMP,MCF5249_SDRAMC_SDCTR,32) /* Write access macros for general use */ #define MCF5249_WR_SDRAMC_SDCCR(IMMP,DATA) \ Mcf5249_iowr(IMMP,MCF5249_SDRAMC_SDCCR,32,DATA) #define MCF5249_WR_SDRAMC_SDCTR(IMMP,DATA) \ Mcf5249_iowr(IMMP,MCF5249_SDRAMC_SDCTR,32,DATA) /* Bit level definitions and macros */ #define MCF5249_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13) #define MCF5249_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13) #define MCF5249_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13) #define MCF5249_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13) /* Do not initialize SDRAM if already running in SDRAM */ if (!(MCF5249_RD_SDRAMC_SDCCR(imm) & MCF5249_SDRAMC_SDCCR_ACT)) { /* Initialize SDRAMC Timing Register for 66MHz operation */ MCF5249_WR_SDRAMC_SDCTR(imm, 0 | MCF5249_SDRAMC_SDCTR_RTP_66MHz | MCF5249_SDRAMC_SDCTR_RC(1) | MCF5249_SDRAMC_SDCTR_RP(3) | MCF5249_SDRAMC_SDCTR_RCD(2) | MCF5249_SDRAMC_SDCTR_CLT_2 ); /* Initialize SDRAMC Control Register for M5249C3 board */ MCF5249_WR_SDRAMC_SDCCR(imm, 0 | MCF5249_SDRAMC_SDCCR_MCAS_A9 | MCF5249_SDRAMC_SDCCR_BALOC_A21 | MCF5249_SDRAMC_SDCCR_REG | MCF5249_SDRAMC_SDCCR_INIT ); }

  13. Support Routines io.c : • character input and output routines using the on-chip UARTs printf.c : • simplified version of standard IO routine printf() stdlib.c : • subset of the C standard library alloc.c : • fixed run-time malloc() and free() routines

  14. Simple Application Empty application template containing: main.c : simple main process int_handlers.c : template for handling interrupts and exceptions Init FAT Simple

  15. FAT Application • Factory Acceptance Test: • Tests the hardware of the M5249C3 including: • SDRAM • Ethernet • Flash • RS-232 terminals • LEDs Init FAT Simple

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