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Code Example

Code Example. LD F6,34(R2) LD F2,45(R3) MULTI F0,F2,F4 SUBD F8,F6,F2 DIVD F10,F0,F6 ADD F6,F8,F2. LD1. LD2. SUBD. MULTI. ADD. DIVD. Operation latencies: load/store 2 cycles, Add/sub 2 cycles, Mult 10 cycles, divide 40 cycle. Tomasulo Example Cycle 0.

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Code Example

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  1. Code Example LD F6,34(R2) LD F2,45(R3) MULTI F0,F2,F4 SUBD F8,F6,F2 DIVD F10,F0,F6 ADD F6,F8,F2 LD1 LD2 SUBD MULTI ADD DIVD Operation latencies: load/store 2 cycles, Add/sub 2 cycles, Mult 10 cycles, divide 40 cycle

  2. Tomasulo Example Cycle 0

  3. Tomasulo Example Cycle 1 Yes

  4. Tomasulo Example Cycle 2

  5. Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations • Load1 completing; what is waiting for Load1?

  6. Tomasulo Example Cycle 4 • Load2 completing; what is waiting for it?

  7. Tomasulo Example Cycle 5

  8. Tomasulo Example Cycle 6

  9. Tomasulo Example Cycle 7 • Add1 completing; what is waiting for it?

  10. Tomasulo Example Cycle 8

  11. Tomasulo Example Cycle 9

  12. Tomasulo Example Cycle 10 • Add2 completing; what is waiting for it?

  13. Tomasulo Example Cycle 11 • Write result of ADDD here vs. scoreboard?

  14. Tomasulo Example Cycle 12

  15. Tomasulo Example Cycle 13

  16. Tomasulo Example Cycle 14

  17. Tomasulo Example Cycle 15 • Mult1 completing; what is waiting for it?

  18. Tomasulo Example Cycle 16 • Note: Just waiting for divide

  19. Tomasulo Example Cycle 55

  20. Tomasulo Example Cycle 56 • Mult 2 completing; what is waiting for it?

  21. Tomasulo Example Cycle 57 • Again, in-oder issue, out-of-order execution, completion

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