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FAST PIPELINED FLOATING POINT UNIT

FAST PIPELINED FLOATING POINT UNIT. MYTHREYI NETHI,. Floating Point Representation. (-1) * 1.f * 2e-bias. s. Hidden bit. Single precision floating point format. 31. 30. 23. 22. 0. Sign. Biased. Significand. exponent. Biased constant is +127. Real Number and Non number Encoding.

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FAST PIPELINED FLOATING POINT UNIT

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  1. FAST PIPELINED FLOATING POINT UNIT MYTHREYI NETHI, Fast Pipelined Floating point Unit Project presentation

  2. Floating Point Representation (-1) * 1.f * 2e-bias s Hidden bit Single precision floating point format 31 30 23 22 0 Sign Biased Significand exponent Biased constant is +127 Fast Pipelined Floating point Unit Project presentation

  3. Real Number and Non number Encoding Fast Pipelined Floating point Unit Project presentation

  4. Rounding bits and Algorithms Rounding bits Guard bit, G Round bit, R Sticky bit, S Rounding Algorithms • Round to Nearest • Round to Zero • Round to Positive Infinity • Round to negative infinity Fast Pipelined Floating point Unit Project presentation

  5. Floating Point Exceptions According to IEEE 754, • Invalid operation • Divide by Zero • Inexact Result • Underflow • Overflow Fast Pipelined Floating point Unit Project presentation

  6. BlockDiagram Floating Point Unit Fast Pipelined Floating point Unit Project presentation

  7. Start Start Compare the two exponents and Shift the smaller number. Compare the two exponents, Shift the smaller number. Add/Sub the two significands Normalize the result by shifting and changing the exponent. Add/Sub the two significands performing rounding in parallel. Any Overflow? Yes Normalize the result by shifting and changing the exponent. No Exception Round the significand Exceptions? Yes No Still Normalized? Exception No Yes Done Done Flowchart Comparison Floating point add/sub Floating point add/sub with rounding in parallel Fast Pipelined Floating point Unit Project presentation

  8. Pre Normalization of Adder/Subtractor Block Fast Pipelined Floating point Unit Project presentation

  9. Addition/Subtraction with rounding in parallel Fast Pipelined Floating point Unit Project presentation

  10. Post Normalization of Adder/Subtractor Block Fast Pipelined Floating point Unit Project presentation

  11. Block Diagram of Multiplication Unit Fast Pipelined Floating point Unit Project presentation

  12. Pre Normalization of Multiplier block • Wallace Tree • Booth Recoding Table Fast Pipelined Floating point Unit Project presentation

  13. Addition of Partial products with rounding in parallel Fast Pipelined Floating point Unit Project presentation

  14. Block Diagram of Divider Unit Quotient Calculation Stage Fast Pipelined Floating point Unit Project presentation

  15. SRT Radix-2 Algorithm Fast Pipelined Floating point Unit Project presentation

  16. SRT Radix-2 Division Fast Pipelined Floating point Unit Project presentation

  17. SRT Radix-4 Division with Two Radix-2 Division Units Overlapped Fast Pipelined Floating point Unit Project presentation

  18. Gradual Underflow Overflow Fast Pipelined Floating point Unit Project presentation

  19. Divide by Zero Exception Inexact Exception Invalid Operation Exception • The inexact exception occurs • if the result of an operation is • not exactly representable in • the single precision format • Any operation on a signaling NaN. • Addition or subtraction :- magnitude subtraction • of infinities such as, • (infinity + (-infinity)), • (infinity-infinity). • Multiplication :- ±infinity × ±infinity, • ±infinity × 0. • Division :- ±0/±0, ±infinity / ±infinity. Fast Pipelined Floating point Unit Project presentation

  20. Conclusions • It was Successfully designed and implemented in XSV-300 • FPGA board. • The clock frequency is around 15MHz to 20 MHz. • The total area is approximately 40%. Fast Pipelined Floating point Unit Project presentation

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