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SoC 설계 기초

SoC 설계 기초. 성균관대 조준동 교수. 목차. 가 . SoC Design Flow 나 . HW/SW Co-design 다 . platform-based design 라 . Network-on-chip 마 . 저전력 설계. 가 . SoC Design Flow. 성균관대 조준동 교수. 목차. SoC 설계 동향 3G 를 위한 설계 방법 설계 플로루 지적재산을 이용한 설계 방법 다양한 설계 방법 형태. SOC.

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SoC 설계 기초

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  1. SoC 설계 기초 성균관대 조준동 교수

  2. 목차 가. SoC Design Flow 나. HW/SW Co-design 다. platform-based design 라. Network-on-chip 마. 저전력 설계

  3. 가. SoC Design Flow 성균관대 조준동 교수

  4. 목차 • SoC 설계 동향 • 3G를 위한 설계 방법 • 설계 플로루 • 지적재산을 이용한 설계 방법 • 다양한 설계 방법 형태

  5. SOC • What are you going to do with that many transistors? Virtual Components Real Components IP Component based design System on a Chip System on Multiple Boards

  6. Shannon Beats More 1M Algorithmic Complexity (Shannon’s Law) 1000 x 2x/3-6 months WAN/MAN Bandwidth 10,000 Log Growth Processor Performance Processor Performance (~Moore’s Law) 2016: 2500 MIPS 100 2x/18 months ‘01 ‘07 97 9 9 ‘03 ‘05 (Source: MorphICs)

  7. 2002 Technology Roadmap 시장전망 (단말기) 3G 350,000 3.5G 4G 300,000 2GHz 3-6Ghz 밴드폭 250,000 14.4Mbps 속도 100 Mbps Revenue(million $) 200,000 다운로드 10MB/200sec 100MB/10sec 150,000 24MbpsX2 Image Bit Rate 385kbps 100,000 에너지 소모량 30-50W 175W 0 2001 2003 2004 2005 2006 2000 Contents 700kbytes 15Mbytes Year *출처 ETRI, 2000 CPU 800 Mhz 5-10GHz 집적도 200M gates 1B gates 2005 1999 2010 2001 2003 2007 - 개인화: Context-aware Sensor Networks - 고속화: NoC 기술 - 저전력화: ACM, PSM, DVS, GC, LCC - 재사용화: Hardware/Software Co-design

  8. Radio systems • WiFi – 10-100Mbits/sec unlicensed band • OFDM, M-ary coding • 3G – .1-2 Mbits/sec wide area cellular • CDMA, GMSK • Bluetooth – .8 Mbit/sec cable replacement • Frequency hop • ZigBee – .02-.2 Kbits/sec low power, low cost • QPSK • UWB – Recently allowed by FCC • Short pulses (no carrier), bi-phase or PPM

  9. Power Dissipation 10 W 802.11a 802.11bg 3G 1 W 100 mW Bluetooth UWB ZigBee 10 mW ZigBee UWB 1 mW 0 GHz 1GHz 2 GHz 3 GHz 4 GHz 5 GHz 6 GHz

  10. Cost (projections) $1000 3G $100 802.11a 802.11b,g UWB $10 Bluetooth ZigBee ZigBee $1 UWB $ .10 0 GHz 1GHz 2 GHz 3 GHz 4 GHz 5 GHz 6 GHz

  11. Data rate UWB 100 Mbit/sec 802.11g 802.11a 802.11b 10 Mbit/sec 1 Mbit/sec 3G Bluetooth ZigBee 100 kbits/sec ZigBee 10 kbits/sec UWB 0 GHz 1GHz 2 GHz 3 GHz 4 GHz 5 GHz 6 GHz

  12. Integration on SOC on CMOS Process

  13. ‘Top Ten Obstacles to 3G Wireless Technology’ from: Carl Panasik “Overcoming Obstacles to 3G Wireless Technology”, Communications System Design, January, 2001, pp. 11-12.. Reused with permission. Carl Panasik is in the Wireless Unit of TI. • Stable Standards • Increased DSP Performance • Software Sophistication • Lower Power Consumption • Advanced Power Management • Increased Battery Capacity • 3G OSes • Enhanced Radio Technology • Cost Concerns • Innovative Applications

  14. Multimedia Cell phone Challenges • 3G WCDMA communications channel • Complexity 5x to 6x greater than GSM • Higher throughput with lower power • Wider bandwidth with increased linearity • Multi-standard capability • Combined challenges of wireless video • Managing BER impacts on video quality • FEC -- forward error correction • Managing bandwidth and video quality • Higher power efficiency • Higher integration -- digital logic, memory, mixed-signal, & RF • Lower cost

  15. · SOC Design Trends • Expected to integrate more and more complex • Web-browsing, real-time video processing, speech recognition and synthesis • Average operating power at or below 100mW and standby power levels at or below 2mW • Performance levels must increase from 300 million operations per second (MOPS) today to 2500 MOPS in 2016

  16. Four main applications • Set-top box: Mobile multimedia system, base station for the home local-area network. • Digital PCTV: concurrent use of TV,3D graphics, and Internet services • Set-top box LAN service: Wireless home-networks, multi-user wireless LAN • Navigation system: steer and control traffic and/or goods-transportation

  17. Achieving functionality while maximizing battery life and minimizing size GPS Noise cancellationheadphones Cochlear implant Cellular phone Medicalwatch Hearing aid Portable audio Digital still camera Digital radio

  18. USB Node Blue Tooth I/O 1394/FireWire V.90 Modem ETHERNET PCI Video/Ch3 RF 3G WCDMA Implementation Choices for a 3G DeviceCadence If I change architecture, what happens to performance? What functions do I integrate? What is my IP supplier chain process? How do I reuse my own IP? What information is required to integrate IP? I/O Channels What IP do I build, what IP do I buy? What do I reuse? Image processing Does the IP integrate throughout the flow? RISC/DSP/ASIC Pixel Defect Masking Demosaic, Gamma RGB-YUV, JPEG I/O & Network Stack Sensor A/D How can I use IP standards? SRAM/DRAM/Flash MEMORY Will this platform meet cost targets? RISC/DSP/ASIC G.723.1/ADPCM Audio Compression Mic A/D Amp MEMORY UNTETHERED CAMERA View Finder LCD Display Photo MEMORY Flash Multilevel Flash Disk, DVD BATTERY RF WIRELESS CHARGER/PWR MGMT IrDA

  19. SoC Design Flow

  20. StructuredSoC Designs • Hierarchy: Subdivide the design into many levels of sub-modules • Regularity: Subdivide to max number of similar sub-modules at each level • Modularity: Define sub-modules unambiguously & well defined interfaces • Locality: Max local connections, keeping critical paths within module boundaries

  21. for (I=0; I<N; I++) a[I] = b[I]*c[I]; ... application software The SoC platform hardware platform

  22. System-on on-Chip components

  23. Common Fabric for IP Blocks • Soft IP blocks are portable, but not as predictable as hard IP. • Hard IP blocks are very predictable since a specific physical implementation can be characterized, but are hard to port since are often tied to a specific process. • Common fabric is required for both portability and predictability. • Wide availability: Cell Based Array, metal programmable architecture that provides the performance of a standard cell and is optimized for synthesis.

  24. Why SOC? • SOC specs are coming from ICT system engineers rather than RTL descriptions • SOC will bridge the gap b/w s/w and their implementation in novel, energy-efficient silicon architecture. • In SOC design, chips are assembled at IP block level (design reusable) and IP interfaces rather than gate level

  25. Types of System-on-a-Chip Designs

  26. Energy-Flexibility Gap 1000 신호처리 ASIC 200 MOPS/mW 100 에너지 효율 (MOPS/mW) 재구성 구조 10-80 MOPS/mW 10 신호처리 프로세서 ASIPs, DSPs 3 MOPS/mW 1 임베디드 프로세서(ARM) 0.5 MOPS/mW 0.1 가용성 6

  27. Physical gap • Timing closure problem: layout-driven logic and RT-level synthesis • Energy efficiency requires locality of computation and storage: match for stream-based data processing of speech,images, and multimedia-system packets. • Next generation SOC designers must bridge the architectural gap b/w system specification and energy-efficient IP-based architectures, while CAE vendors and IP providers will bridge the physical gap.

  28. Circular Y-Chart

  29. Implementing Digital Systems

  30. The 100 Million Transistor Question HOW BEST CAN WE USE THEM TO SOLVE OUR COMPUTING PROBLEMS ?

  31. Answer I: Multiprocessor on a chip Requirement: Efficient, parallelizing compiler Problems: Enough parallelism in programs? Does not go fast enough for video applications, for instance.

  32. Answer II: Giant FPGA Requirement: CAD system for FPGAs Problems: May work well for bit- level video computations, but in general FPGAs are inefficient.

  33. Answer III: H/W and S/W Co-design

  34. ASIP Design • Given a set of applications, determine micro architecture of ASIP (i. e., configuration of functional units in datapaths, instruction set) • To accurately evaluate performance of processor on a given application need to compile the application program onto the processor datapath and simulate object code. • The micro architecture of the processor is a design parameter!

  35. ASIP Design Flow

  36. Alternatives for Semiconductor • Quantum Computing • DNA Computing • Optical Computing • Molecular Computing

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