Lecture 3. Virtual Platform and ARM Introduction

1. ECM586 Special Topics in Embedded Systems Lecture 3. Virtual Platform and ARM Introduction Prof. Taeweon Suh Computer Science Education Korea University

2. Virtual Platform • Virtual Platform is a software model of a whole computing system • Virtual Platform is very widely used for software development much before hardware is ready • The target computing systems of virtual platform have been SoCs (System-on-chip), but it can be used for future PC systems • Don’t be confused with Virtual Machine! • VM allows the sharing of the underlying physical machine resources between different virtual machines, each running its own OS • The software layer providing the virtualization is called a virtual machine monitor or hypervisor • x86 provides several instructions for virtualization

3. Software models Software running on new products SoC model in 2010 • Firmware and RTOS porting to SoC • Applications on SoC PC system model in 2010 • BIOS, Firmware and OS development • Validation software development Virtual Platform (Cont.) Your PC

4. Virtual Machine • Example: Xen

5. SoC Market Dynamics SNUG: Synopsys Users Group Source: Synopsys

6. SoC Design Challenges Source: TLM2.0 presentation from CoWare

7. Software Determines Project Schedules Source: Synopsys

8. Advantages of VP Source: Synopsys

9. How is it different from simulators? • In a broader sense, all the simulators may be viewed as virtual platform • Benchmarks and testvectors are running on virtual models (simulators) • However, simulators tend to model only specific components rather than a whole system (platform) • For example, Simplescalar doesn’t model peripheral devices. So, it is not feasible to run BIOS, DOS, OS (Windows) • http://www.simplescalar.com/

10. How fast VP should run? • Performance comparisons of simulation, emulation, and virtual platform • Hardware simulation • Concurrent modeling • ~ IPS (Instruction / second) • Hardware emulation • Porting RTLs into reconfigurable machine (array of FPGAs (Field Programmable Gate Array) • KIPS ~ MIPS depending on what you emulate • Virtual platform • ~MIPS • Able to run real-applications on top of OS in reasonable time

11. How to model VP? • Depending on the level of accuracy you want to achieve and your goal, there are different levels of abstractions • Level of abstractions • Cycle accurate model (CA) • Verification and HDL co-simulation • Programmer’s view model (PV, we focus on PV) • Highly abstracted mode • Register accurate model • Functionally correct

12. What Language to model VP? • Verilog-HDL and VHDL • Used to model cycle-accurate model • Too slow (~IPS depending on complexity) • C, C++ • Used to model PV in general • Also can be used for cycle-accurate modeling

13. In this class…. • We are going to use a software model for a small SoC called AT91 from Amtel • http://www.atmel.com/

14. AT91x40

15. Block Diagram of AT91x40

16. Let’s focus on CPU (ARM7TDMI) first and come back later to the system block diagram

17. ARM (www.arm.com)

18. ARM Source: 2008 Embedded SW Insight Conference

19. ARM Partners Source: 2008 Embedded SW Insight Conference

20. ARM Source: 2008 Embedded SW Insight Conference

21. ARM Processor Portfolio Source: 2008 Embedded SW Insight Conference

22. Abstraction • Abstraction helps us deal with complexity • Hide lower-level detail • Instruction set architecture (ISA) • An abstract interface between the hardware and the low-level software interface

23. Abstraction Analogies Driver Customer Abstraction layer Abstraction layer Machine Details Machine Details Hardware board in a vending machine Combustion Engine in a car Break system in a car

24. Abstraction in Computer Users Application programming using APIs Provides APIs (Application Programming Interface) Abstraction layer Operating Systems Instruction Set Architecture (ISA) Machine language Assembly language Abstraction layer Core0 Core1 Hardware implementation L2 Cache

25. Levels of Program Code (MIPS) • High-level language program (in C) swap (int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } • Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 • Machine (object, binary) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 . . . one-to-many C Compiler one-to-one Assembler

26. Levels of Program Code (x86) Code with High-level Language Machine Code a = 3; c7 45 f0 03 00 00 00movl $0x3,-0x10(%ebp) b = 9; c7 45 f4 09 00 00 00 movl $0x9,-0xc(%ebp) c = a + b; 8b 55 f4 mov -0xc(%ebp),%edx 8b 45 f0 mov -0x10(%ebp),%eax 01 d0 add %edx,%eax 89 45 f8mov %eax,-0x8(%ebp) int main() { int a, b, c; a = 3; b = 9; c = a + b; return c; } C Compiler Instructions (human-readable) Representation in hexadecimal (machine-readable)

27. High-Level Code is Portable int main() { int a, b, c; a = 3; b = 9; c = a + b; return c; } Compile Compile X86-based Notebook (CPU: Core 2 Duo) PowerBook G4 (CPU: PowerPC)

28. CISC vs RISC • CISC (Complex Instruction Set Computer) • One assembly instruction does many (complex) job • Variable length instruction • Example: x86 (Intel, AMD) • RISC (Reduced Instruction Set Computer) • Each assembly instruction does a small (unit) job • Fixed-length instruction • Load/Store Architecture • Example: MIPS, ARM

29. ARM Architecture • ARM is RISC (Reduced Instruction Set Computer) • x86 instruction set is based on CISC (Complex Instruction Set Computer) even though internally x86 implements pipeline • Suitable for embedded systems • Very small implementation (low price) • Low power consumption (longer battery life)

30. ARM Registers • ARM has 31 general purpose registers and 6 status registers (32-bit each)

31. ARM Registers • Unbanked registers: R0 ~ R7 • Each of them refers to the same 32-bit physical register in all processor modes. • They are completely general-purpose registers, with no special uses implied by the architecture • Banked registers: R8 ~ R14 • R8 ~ R12 have no dedicated special purposes • FIQ mode has dedicated registers for fast interrupt processing • R13 and R14 are dedicated for special purposes for each mode

32. R13, R14, and R15 • Some registers in ARM are used for special purposes • R15 == PC (Program Counter) • x86 uses a terminology called IP (Instruction Pointer) • “EIP” register • R14 == LR (Link Register) • R13 == SP (Stack Pointer)

33. CPSR • Current Program Status Register (CPSR) is accessible in all modes • Contains all condition flags, interrupt disable bits, the current processor mode

34. CPSR bits

35. CPSR bits

36. CPSR bits • ARM: 32-bit mode • Thumb: 16-bit mode • Jazelle: a special mode for JAVA acceleration

37. Interrupt • Interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. • Hardware interrupt causes the processor (CPU) to save its state of execution via a context switch, and begin execution of an interrupt handler. • Software interrupt is usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. • Interrupt is a commonly used technique in computer system for communication between CPU and peripheral devices • Operating systems also extensively use interrupt (timer interrupt) for task (process, thread) scheduling

38. Hardware Interrupt in ARM • IRQ • Normal Interrupt Request by asserting IRQ pin • Program jumps to 0x0000_0018 • FIQ • Fast Interrupt Request by asserting FIQ pin • Has a higher priority than IRQ • Program jumps to 0x0000_001C IRQ FIQ

39. Software Interrupt in ARM • There is an instruction in ARM for software interrupt • SWI instruction • Software interrupt is commonly used by OS for system calls • Example: open(), close().. etc

40. Exception Vectors in ARM

41. Exception Priority in ARM