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LISARM: embedded ARM platform design and optimization

Esame di Laurea in Ingegneria Elettronica (Vecchio Ordinamento) Sessione di Aprile 2007. LISARM: embedded ARM platform design and optimization. Relatori: Prof. Guido Masera Ing. Maurizio Martina Ing. Fabrizio Vacca Candidato: Carlo Ceriani. Summary. ASIPs introduction

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LISARM: embedded ARM platform design and optimization

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  1. Esame di Laurea in Ingegneria Elettronica (Vecchio Ordinamento) Sessione di Aprile 2007 LISARM: embedded ARM platform design and optimization Relatori: Prof. Guido Masera Ing. Maurizio Martina Ing. Fabrizio Vacca Candidato: Carlo Ceriani

  2. Summary • ASIPs introduction • LISATek toolsuite and LISA language • ARM7TDMI architecture • LISARM model • Toolchain adaption and memory interfacing • Conclusions and future applications Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  3. ASIP introduction • System-on-Chip (SoC) trend • Hardware-Software partitioning • Programmable platforms: embedded processors and FPGAs • Extensible Instruction Set Architecture approaches • Architecture Specific Instruction-set Processors (ASIPs) Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  4. LISATek toolsuite • Architecture Description Language (ADL) • LISA 2.0: Language for Instruction Set Architecture • Modeling tools: • Processor Designer, Instruction-set Designer, Syntax Debugger • Software application development tools: • C-compiler, assembler, disassembler, IS-simulator • Synthesizable HDL hardware description Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  5. ARM7TDMI characteristics • 32-bit Von Neumann RISC architecture • 3-stage pipeline and prefetching • Privileged operating modes and exception handling • Interrupt management • Thumb micro-architecture • Coprocessor interface Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  6. LISARM model • Instruction-accurate model: • instruction syntax and coding • instruction micro-code • Cycle-accurate model: • pipeline execution and polling operations • Description style: hardware behavior focusing • ALU, barrel shifter and multiplier description • Exception handling and interrupt management Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  7. LISARM model: instruction-set • Data processing instructions: • flexible second operand and barrel shifter operations • multiply/multiply and accumulate instructions • Data transfer instructions: • single data: 8 addressing modes • flexible offset • byte/halfword, signed/unsigned data transfer • block data transfer: 8 stacking modes • data swap instruction • Branch and PSR transfer instructions • No coprocessor instructions Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  8. Memory wrapper • Problem: ARM byte addressing Byte Select Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  9. pre-assembler post-disassembler LISARM toolchain adaption • Problem: ARM assembler capabilities • “immed8_r” immediate operand format • block data transfer register list Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  10. Generated hardware description • VHDL description: • instruction decoder • pipeline controller and distributed logic • other controller units • datapath: ALU, barrel shifter, 32x8 multiplier • LISA operations and hardware optimization • ModelSim simulations and verification • HDL synthesis phase Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  11. Conclusions • ARM-like instruction-set platform: • software development tools and synthesizable VHDL • Complexity tackling by using LISA mechanisms: • decoding process • pipeline events and operation scheduling • Simple micro-architecture functionalities description: • “C-style” language micro-code • Code reuse for architecture update/evolution: • time/effort saving • development tools from a unique LISA description Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  12. Possible future applications • Instruction-set extension/reduction • Micro-architecture optimization: • micro-code modification • Thumb instruction-set implementation: • code compaction improvement • full 32-bit architecture capabilities • Harvard architecture Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  13. FE/DC DC/EX MEMORY FE DC EX FE/DC DC/EX DC/MEM INSTRUCTION MEMORY FE DC EX DATA MEMORY MEM Harvard architecture Carlo Ceriani - LISARM: embedded ARM platform design and optimization

  14. Thanks for your attention! Jaume Plensa: “Poet’s Chair” Any question? Carlo Ceriani - LISARM: embedded ARM platform design and optimization

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