Software / Hardware Co-Design of a JPEG Encoder Team Members: Joe Salemi Brandon Sterner

1. Software / Hardware Co-Design of a JPEG EncoderTeam Members:Joe SalemiBrandon Sterner

2. What is Software/Hardware Co-Design? • Using software and hardware in parallel to execute a given application, with the goal of increasing overall performance. • SW/HW co-design may effectively be applied to any application that is both computationally intensive and can be partitioned into separate units.

3. Baseline DCT-JPEG Encoding Algorithm • JPEG Encoding involves using DCT (Discrete Cosign Transforms) operations, which can involve roughly 300 floating point operations each. Encoding a JPEG file usually involves thousands of DCT operations. • Our hypothesis is that if we were to partition the DCT operations out and execute them with FPGA’s working in parallel with a PC, application performance would be greatly increased.

4. Baseline DCT-JPEG Encoding Algorithm • Initial image file is a PPM (Portable Pixel Map). This format was chosen because the data is stored as integer RGB values. • Separate image into three color planes, RGB. • Convert the color planes to the YIQ color space, which takes better into consideration some known facts about the human vision. • Each color plane subdivides into sub regions of 8 x 8 pixels each. • A two dimensional discrete cosine transform (DCT2) is then applied to each 8 x 8 sub region separately. The matrices are now in the frequency domain. Since the transformation matrix is band-limited, only 8 x 8 = 64 frequency components are included in the result. • Each 8x8 matrix is then scaled by an 8 x 8 matrix Q (known as the quantization matrix), which is determined by empirical studies of human visual perception. Since the human eye is more perceptive to lower frequencies than to higher frequencies, the idea is to scale the amplitude of each frequency by a quantization factor to eliminate the higher frequencies. • Each sequence is then encoded using Huffman compression.

5. Baseline DCT-JPEG Encoding Algorithm

6. Equipment • Purple Box • A small purple 486 computer running at 100MHz • Digilent Digilab 2 development board • Xilinx Spartan 2 XC2S200 FPGA • 200,000 gate FPGA, 143 user IO pins • Digilent DIO Module • Switches, Push Buttons, LEDs, Seven Segment Displays, etc. • Digilent Memory Module • Two 512KB SRAM banks • Development PC with Tornado for monitoring the timing of the system.

7. Diamond Prometheus Development Kit

8. Digilent Digilab 2

9. Digilent Memory Module and DIO Board

10. Block Diagram of System • Communication: • Communication between PC and “Purple Box” is over the RIT network. • “Purple Box” is connected to the FPGA via a LPT1 • SRAM module is connected to D2 expansion slot

11. User Interface • Command Line Interface • Used for starting • Displaying timing data • Displaying Errors • Status Lights (FPGA) • Idle • Computing • Memory Transfers • Image Viewing - Uncertain • Would prefer to send resulting JPEG file back to the development PC. This depends on whether SE security policy will allow us to do this. • Alternative would be to display the image directly from the purple box. This depends on whether the difficulties can be resolved in downloading the new version of VxWorks onto the “purple box”.

12. Progress/Timeline • PurpleBox File System Testing Done • PurpleBox Parallel Port Testing Done • Software Implementation In Progress • Hardware Implementation In Progress • Testing and Analysis of Results

13. Hardware Costs

14. Software • WindRiver VxWorks • WindRiver Tornado • Xilinx ISE 6.0 • Matlab

15. Difficulties • File IO • By default, redirected to FTP • Remember to close files • Purple box crashing • Unexplainable crashes • SE security policy • Can’t write to C drive • FTP policy

16. Questions ?