1 / 3

Signal Buffer

LUCID TRIGGER BOARD (1 unit + spares) – VME 9U. s-LINK Busy. s-LINK. Scaler units (fulfil lumi group requests). to ROS. 160 MB/s. 1. Signal Buffer. LVDS 1_1. D e t e c t o r 1. >200 Bytes/ev. 2. LVDS 1_2. FPGA based TRIGGER PROCESSING UNIT. 43. LVDS 22_1. VME I.F. 44.

dustin-moon
Download Presentation

Signal Buffer

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. LUCID TRIGGER BOARD (1 unit + spares) – VME 9U s-LINK Busy s-LINK Scaler units (fulfil lumi group requests) to ROS 160 MB/s 1 Signal Buffer LVDS 1_1 D e t e c t o r 1 >200 Bytes/ev 2 LVDS 1_2 FPGA based TRIGGER PROCESSING UNIT 43 LVDS 22_1 VME I.F 44 LVDS 22_2 Max 44 ser. Inp 594 bit/BX VME P1 Max 44 ser. Inp 594 bit/BX 1 D e t e c t o r 2 LVDS 23_1 2 LVDS 23_2 Signal Buffer 43 LVDS 44_1 44 LVDS 44_2 CTRL LOGIC opt. lnk from TTCIX TTCRQ i.f. to the L1 trigger

  2. LARRY (LUCEDRO) TRIGGER BOARD – VME 9U s-LINK Busy s-LINK Scaler units (fulfil lumi group requests) to ROS 160 MB/s 1 LVDS 1_1 D e t e c t o r 1 ~200 Bytes/ev 2 LVDS 1_2 Mezzanine FPGA based TRIGGER PROCESSING UNIT 43 LVDS 22_1 VME I.F 44 LVDS 22_2 44 ser. Inp 594 bit/BX VME P1 44 ser. Inp 594 bit/BX 1 D e t e c t o r 2 LVDS 23_1 2 LVDS 23_2 Mezza nine Tracks from AM 43 LVDS 44_1 FIFO 44 LVDS 44_2 opt. lnk from TTCIX CTRL LOGIC TTCRQ i.f. Hits to AM Clock BX CTRL ? TRIGGER

More Related