CMS Level 1 Global Trigger upgrade

1. CMS Level 1 Global Trigger upgrade First proposal to implement the Central Trigger Control with MTCA boards Institut für Hochenergiephysik, Vienna A.Taurok, B. Arnold, H.Bergauer, M. Eichberger, T. Schreiner 12. March, 2010

2. Custom Backplane 6 7 8 9 1 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 CAEN VME CONTROLLER PSB PSB PSB PSB PSB PSB PSB FREE VME FREE VME L1A_OUT L1A_OUT TCS spare TIM GTFE GMT FDL GTL 128 Algo L1A TOTEM 8 RPC muons 4 DT muons 4 CSC muons CLK, ORBIT PC: RUN Control 4TAU-JET, ET*, JetNr, 4IEG, 4EG, 4JET, 4fJET (ET*=total ET, HT, MET) MIP/QUIET bits Detector subsystems TECHNICAL TRIGGER SIGNALS TTC - GPS-TIME S-links: DAQ, EVM aTTS DAQ APV-EMULATORS STATUS SIGNALS LEVEL 1 GLOBAL TRIGGER 9U-VME CRATE Version 2008

3. TCS interfaces • Output (L1A, BGo(3:0), Strb, BCR, CLK) to 32 partitions (TTCci boards) • 2 GT_conversion boards: MTCA format: double width, full height (148.8x28.95x181.5 mm) • Front panel assembly: • 1 optical link • 16 HR25-9R-16PA connectorson small board of 120x28 mm, • edge connector to MTCA board for 128 differential signals • STATUS input from 32 Partitions (FMM boards) • 2 GT_conversion boards (standard front panel assembly) • 1 optical link • 16 RJ45 edge connectors • STATUS input from 8 Emulators & Signals (L1A, BCR,…) to 8 Emulators • 1 GT_conversion board (standard front panel assembly) • 1 optical link • 16 RJ45 edge connectors • Input from Global Trigger Processor (4 Status bits, 8 FinalOR, BCRES, CLK) • & STATUS inputfrom 8 DAQ partitions • 1 GT_conversion board (standard front panel assembly)

4. Serial link Serial link FPGA FPGA FPGA FPGA FPGA FPGA 64 bits/40MHz 64 bits/40MHz Serial link Serial link Serial link Serial link 64 bits/40MHz 64 bits/40MHz 64 bits/40MHz 64 bits/40MHz Central Trigger Control implemented with MTCA boards CTC board Off the shelf (?) MTCA board with ~8 optical links Optical links Simple GT-interface board 9U VME mounted in TCS slot of actual Global Trigger Crate L1A, BGo, … to 32 TTCci STATUS from 32 FMM 8 FinalOR 4 GT-status bits BCRES STATUS from 8 EMULATORS L1A,BCR… to 8 EMULATORS STATUS from 8 DAQ

5. MTCA Micro Telecommunications Computing Architecture Crate examples Example: Single width shelf (Schroff/Pentair) Example: Double width shelf (Schroff/Pentair) Serial Links; PCIe, Ethernet, RapidIO,.. Hot swap Intelligent Peripheral Management Interface (IPMI) (platform) PM power module:12V, 3.3V ≤12 AMC advanced mezzanine card Single width: 73,50 mm x 180,60 mm Double width: 148.8 mm x 180,60 mm MCH MicroTCA Carrier Hub MTCA = Micro Telecommunications Computing Architecture 2006 ATCA = Advanced Telecom Computing Architecture PICMG (PCI Industrial Computer Manufacturers Group Single width shelf

6. FPGA FPGA FPGA 40 MHz LVDS to Serial Conversion AMC double width module & standard MTCA backplane • FPGA options: • cheap FPGA (Spartan3A) + ser/par converter • or small Virtex5 chip CONVERSION card double width,full size (w=148.8 mm, l=181.5 mm, h=28.95 mm) FPGA content: parallel/serial converter, Control logic (Ethernet / PCIe) monitoring, synchronization, … LC duplex LVDS - INPUT MODE LVDS -OUTPUTMODE LVDS -I/OMODE Serial link (3.2 Gbps required) Serial link (3.2 Gbps required) Serial link (3.2 Gbps required) 64 bits/40MHz 64 bits/40MHz 64 bits/40MHz Synchronization, Monitoring Monitoring Emulator interface Global Trigger: 128 Technical Trigger bits  2 CONVERSIONboards (INPUT mode) Central Trigger Control: 32x4 STATUS bits  2 CONVERSIONboards (INPUT mode) 8x4x2 EMULATOR CTRL+STATUS  1 CONVERSIONboards (I/O mode) 32x8 L1A+BGo signals  4 CONVERSIONboards (OUTPUT mode) • 9 boards • Serial links (3.2 Gbps) on front panel