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Trigger Upgrade

Trigger Upgrade. Valerie Halyo. Outline. Motivation for the upgrade Plans production and commissioning TSF status ZPD status Interface cards DCT software Detailed preliminary commissioning. Physics. z 0 of all tracks in L-1 events. Background. DCT Upgrade – Motivation.

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Trigger Upgrade

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  1. Trigger Upgrade Valerie Halyo

  2. Outline • Motivation for the upgrade • Plans production and commissioning • TSF status • ZPD status • Interface cards • DCT software • Detailed preliminary commissioning

  3. Physics z0 of alltracksin L-1events Background DCT Upgrade – Motivation Goal: reduce the L1 trigger rate due to beam-related background by cutting on track z0

  4. General Goals • Jun/16 : Parallel commissioning of new DCT connected to one quadrant of the DCH. • Oct/03 : Full commission of the new DCT in parallel to current system including test of the new trigger • Dec/03 : Switch to the new DCT triggering BaBar

  5. Future configuration • Current DCT use only r-f information • New DCT expands this to 3-D • ZPD replaces PTD to add 3-D track fitting • TSF must ship fine-f info for stereo layers  New TSF • Interface cards (TSFi, ZPDi, GLTi) handle added signals BLTi BABARDriftChamber BLT Level-1Accept TSFi ZPDi GLTi TSF ZPD GLT

  6. New Hardware • Mini detector in the GltLab allows us full algorithm and calibration • tests. • New DctOnline code is added and being tested in the Lab and IR2 • Reconfiguration of the Glt during the shutdown

  7. Commissioning Readiness • Goal: Instrument one quadrant of the DCH • Needed for full pT acceptance Learn as much as we can from the beams in June Continue usefulsystem tests during the shutdown z

  8. TSF Status • One prototype assembled • with 3 FPGA • The input Formatter and FCT • chip are fully tested • Algorithm engine is being tested • DAQ was tested in the simulator • not on the board yet but • no conceptual problem anticipated. • Configuration loaded from flat • file was tested successfully • Few prototype boards are supposed • to arrive today. • Production during the shutdown

  9. ZPDi ZPD 153 segments MegaBus Receiver/Driver AlgorithmEngine 0 AlgorithmEngine 1 AlgorithmEngine 2 AlgorithmEngine 3 AlgorithmEngine 4 AlgorithmEngine 5 Fit Results DecisionModule 4 to GLT 8-bit decisions C-link FCCDecoder FPGAConfig Memory access, DAQ control, etc. D-link ZPD Status: • Design and Prototype • Testing • Algorithm test with • MC events: no bit errors • 2. DAQ firmware in • progress • Production: • 13 Production PCB’s were made • 2 loaded and tested • 1 at SLAC 1 in Harvard

  10. ZPDi GLT ZPD TSFi TSF TSFi GLTi TSFi TSF TSFi TSF TSF Interface Cards BLT BLTi TIOM DCC SlowMon TSFi : Arrive early next week. ZPDi: Will arrive during the run Glti: Is tested in teststand. (No for June) IFR EMT

  11. DAQ/Online Software L1DctCalOep L1DctCalOdf L1DctTeststand L1DctOep L1DctCalOnline L1DctOdf L1DctDiagOnline L1DctOnline

  12. Online • All Configurations of the new DCT will be loaded from XTC • or flat ascii files • Double the DCT data: • Every module TC is doubled having two different TC id’s • for production and parasite TC • 1. New ZPD TC and Fex exist and tested • 2. For the TSF Fex is in progress (L1Accept Action almost • ready) • 3. The additional TC’s are transparent to the current system • The new Online code will able to handle two TSF type in one • ROM

  13. New Setup DCH TSFY TSFX/Y DAQ BLT/PTD GLT BLT/ZPD TSFX Rack 23 Rack 24 Rack 25

  14. Operation schedule • June 16: • We are probably going to start by commissioning DCT • Corresponding to 1/8 of DCH namely 2TSFX + 1TSFY • We are going to run parallel but only the current system will trigger. • Occupy rack 25 in the EH with 2 crates in June • The rack is already powered and today the hit exchange • was installed • might have data taking with one ROM handling both TSFX,Y • This configuration enable a use of 3 instead of 4 ROMS • We are getting one DCH DAQ crate for hosting all the roms

  15. Operation schedule • Once TSF FEX is ready we will request an online build • and would like to request COSMIC run hopefully next week • Split all 24 DCH Glink (TIOM->TSFi) to supply DCH data • to old and new TSF • The patch panel to hold the splitters are almost ready • Part of the fiber splitter arrived today • DCT SlowMon for the fiber optical yield was installed but is being debugged with Ray’s slow mon teststand. • In the earliest opportunity we will move to the DCH-MON IOC • We are making full system test at the DCH-DCT teststand at the • GltLab in central Lab before coming to IR2 • (DCH-proto TSF old/new BLT ZPD MasterCrate)

  16. Shutdown Plan • TSF board will be in production • Continue studying and testing the boards and study the result • of this parallel run • Paul .D. has the conceptual design for the new EMT patch panel • which will be done by Paul S. • Su Dong is going to remove the extra 80ms from the BLT/GLT • and add about 8ms for the reading the data to prevent the • corruption of the fifth event coming • Many Thanks to all dataflow (Chris, Matt,Amadeo) • for their continuous help • Thanks to Ray R. Lupe S. Gibson L. Mark F. Jim H.

  17. Potential Issues • We are going to run parallel but the question is • How are we still affecting the main stream • Oep will ignore any damage from the new DCT • so that data logging wont be affected.(report the damage in Jas) • If the dead time cause by New DCT • increases our crate should be taken out of the crate mask • Reframing of the new TSF : • In event of any significant reframing rate (one per minute) • take out the New DCT • Automatic detection of the board will be in both boot and configure • code

  18. Inputs Up to 12 seeds • Each ZPD receivesdata from 9 TSFs • 3/8 in f • Seed segments inthe middle 1/8 ofSL7 and SL10 • 14 bits × 153 segments/CLK4 • Challenge 1: Moving around 8 Gbit/s • Backplane: 153 pins @ 60 MHz • Megabus: 75 LVDS pairs @ 120 MHz 1: mask4: cell location6: f in the cell3: error in f 144used

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