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XC9500XL Architecture

XC9500XL Architecture. CPLD Product Applications. TIB_archB1. XC9500XL Overview. Superset of XC9500 CPLD Optimized for 3.3V systems compatible levels with 5.0/2.5V High f MAX = 200 MHz Fast t PD = 4 nsec Best ISP/JTAG support Best pinlocking Advanced Packaging. Agenda. Overview

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XC9500XL Architecture

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  1. XC9500XLArchitecture CPLD Product Applications TIB_archB1

  2. XC9500XL Overview • Superset of XC9500 CPLD • Optimized for 3.3V systems • compatible levels with 5.0/2.5V • High fMAX = 200 MHz • Fast tPD = 4 nsec • Best ISP/JTAG support • Best pinlocking • Advanced Packaging

  3. Agenda • Overview • Technology • Architecture • ISP • Electrical Compatibility • Support • Family

  4. Features Each macrocell independently selects clock source and phase inversion Clock enable at each macrocell Hysteresis on all inputs Pullup/Bus Hold Option on Pins at power on Expanded Function Block Inputs

  5. Technology • 0.35 micron FastFLASH technology • 4 Layers of Metal • Optimized for high speed 3.3V systems • Ideal for ISP CPLDs • Reprogramming Endurance = 10,000 • Charge Retention = 20 years

  6. Flash vs E2 Endurance Flash delivers: - highest quality - no speed degradation - 20 year retention - reliable reprogramming - worry free field upgrade

  7. Architecture • Uniform • Identical Function Blocks • Identical Macrocells • Identical I/O pins • Abundant Global/Product Term Resources • Great synthesis results • Best pinlocking results

  8. CPLDs PAL Swi- tch Mat- rix PAL • XC9500XL devices are similar to having multiple PAL devices interconnected in one chip • Best applications • Wide functions • Complex counters • Complex state machines • PAL/GAL or TTL integration • Non-volatile • BUS Interface/Control PAL PAL Prog. AND array Fixed OR array FF/ Macro- cell FF/ Macro- cell

  9. High Level Architecture

  10. FastCONNECT II Switch Matrix • Very High Speed Switch Matrix • Greater connectability for all signals • High routability at high utilization • Software delivers high speed automatically • Substantial power reduction

  11. Function Block 54 Inputs Highest FB Fanin

  12. Macrocell

  13. Product Term Allocation 3 available here 2 p-terms required here 5 available here 5 native p-terms Total = 18 requires 2 X tpta delay added to tPD 5 available here

  14. Industry’s Best Pin-Locking Product Term Allocator allows any product term to be borrowed by any macrocell in the same function block Product Term Allocator allows for timing to be held for small to medium logic changes Footprint compatibility allows for easy migration to larger or smaller devices using the same device package

  15. Why Pin-Locking is Necessary The major advantages of In System Programming can only be realized with field-upgrades It does not make sense to do field upgrades if the board needs to be re-worked for minor logic changes It does not make sense to do field upgrades if timing cannot be met

  16. Pin Locking vs Pin Preassignment The software should be allowed to make first pass pin assignments Pre-assigning pins can lead to timing and density underutilization

  17. ISP • Original XC9500 JTAG and ISP instructions: • Program Erase Verify Blankcheck • ID Code Usercode • Intest Extest Hi-Z Bypass • New instruction: • CLAMP • permits pin by pin definition of logic level during bypass • Added S/W support with XACT M1.5 • CPLD and FPGA download via JTAG

  18. Bus Hold Logic • A weak latch holds last state on I/O • RBH= 50kOhms

  19. Bus Hold Logic • Two modes of operation • User mode: Holds last state • ISP or blank device: pull-up resistor • Better than just a pull-up resistor • eliminates slow changing of bus signals during hi-z • reduced system power during hi-z

  20. Voltage Compatibility VCCINT = 3.3V VCCIO = 3.3V/2.5V CORE LOGIC Note: output p-channel gives full rail swing

  21. Voltage Compatibility 3.3/5V 5V 3.3V VCCIO VCCINT 5V 3.3V Any Any 3.3V XC9500XL 5V TTL 3.3V 3.3V device device

  22. Voltage Compatibility 3.3V/2.5V 3.3V 2.5V VCCIO VCCINT 3.3V 2.5V Any Any 3.3V 2.5V XC9500XL 2.5V 2.5V device device

  23. XC9500XL Voltage Compatibility Summary EIA Standard Voltage Levels No Power Supply Sequencing Restriction

  24. Input Signal Hysteresis VOH 50 mV VOUT (VOLTS) VOL 1.45V 1.40V VIN (VOLTS)

  25. Power Optimization • Minimum of 67% decrease in power over 5V CPLDs • Low power option per macrocell • Even lower power if I/Os swing 0-2.5V • FastCONNECT II lower power than XC9500 • I/Os swing full VCCIO range with p-channel pullups (shuts off attached external logic)

  26. XC9500XL Design Software • XC9500XL Fitters in all Xilinx Standard S/W Packages • Foundation M1.5 • Alliance M1.5 • Support for Schematics, Verilog, VHDL, Abel • Exemplar • Synopsys • Synplicity • more

  27. XC9500 XC9500 XC9500 Programming Flexibility • Mount XC9500/XL device to PCB, fixing pinouts • Program via download cable (no programmer required) • Recompile design, erase & reprogram multiple times • Debug logic with extended JTAG test • XC9500/XL advantages • Pin-locking architecture maintains pinouts • Endurance of 10,000 cycles • Extended JTAG test ISP Download Cable

  28. Expanded Manufacturing Capability • Mount XC9500/XL and program using standard manufacturing automatic test equipment and JTAG • Board test using IEEE 1149.1 compliant JTAG • Implement last-minute design changes • XC9500/XL advantages • Fast program time (~1 second XC95144XL) using Automated Test Equipment (ATE) • Excellent pin-locking for last-minute design changes • Complete IEEE 1149.1 JTAG

  29. Third Party ATE Support • Hewlett-Packard • Teradyne • Gen-RAD • Common Support for both Xilinx FPGAs and CPLDs.

  30. XC9500XL Family

  31. Conclusion XC9500XL is the CPLD family that meets your leading-edge system needs

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