A Quasi-Delay-Insensitive Method to Overcome Transistor Variation

1. A Quasi-Delay-Insensitive Method to Overcome Transistor Variation Charlie Brej APT Group University of Manchester VLSI 2005

2. Overview • Synchronous Problems • Asynchronous Logic • Why? • How? • Asynchronous Benefits • Delay Insensitivity • Early Output VLSI 2005

3. Problems: Communication • Communication horizon • “For a 60 nanometer process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997] • Clock distributed using wave pipelining VLSI 2005

4. Can’t keep ramping up the clock • Intel pulls the plug on 4GHz Pentium 4 • AMD and Intel using PR based model numbers • New ranges run at much slower clock rate • Higher concentration on parallel execution • Hyper-threading • Multiple cores VLSI 2005

5. Problems: Performance Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Cycle time Worst – Average case performance Real Computation VLSI 2005

6. Clock! What is it good for? • No arguing with the clock • 9am - 5pm. No excuses! VLSI 2005

7. Bundled-Data • When you finish, do the next task • Flexitime Request + Delay Acknowledge VLSI 2005

8. Remove the Clock Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Worst – Average case performance Cycle time Real Computation VLSI 2005

9. How do you know when you are finished? • Synchronous: • Estimate • Global timing reference • Asynchronous (bundled-data) • Estimate • Local delay elements • Asynchronous (delay-insensitive) • When the data arrives • Intrinsic VLSI 2005

10. Becoming Delay Insensitive • Dual-Rail • Two wires • 00 – NULL • 01 – Zero • 10 – One • (11 – Not used) • Four Phase handshake • Return to zero R0 R1 Ack VLSI 2005

11. Delay Insensitivity • No assumptions on speed of wires or gates • Environmental effects • Heat • Voltage supply • Manufacturing defects • Thin Film Transistor • Next generation process sizes VLSI 2005

12. Dual-Rail interfaces Output generated as early as possible Two Early output cases If either input is ‘0’ then the output is ‘0’ Early Output Logic VLSI 2005

13. Bit level pipelining • Forward completed parts of the result • Pace work • Don’t stall parts unless you have to VLSI 2005

14. Bit level pipelining • Forward completed parts of the result • Pace work • Don’t stall parts unless you have to VLSI 2005

15. Early Output cases VLSI 2005

16. Paper contribution • With missing inputs still generates results • Isolates late inputs • Allows next data phase VLSI 2005

17. Remove Unnecessary computation Unbalanced Stages Clock overheads Clock Skew/Jitter Transistor Variability Timing Assumption overheads Signal Integrity Worst – Average case performance Unnecessary Computation/Delays Real Computation Cycle time VLSI 2005

18. Summary • Asynchronous • Delay Insensitive • Safe • No timing assumptions • Average case performance • Remove unnecessary computation VLSI 2005