Key MIPS R2000 Instructions

1. Key MIPS R2000 Instructions • Arithmetic • ADD, SUB, ADDI, MULT, MULTU, DIV, DIVU (U:unsigned) • Logical • AND, OR, NOR, ANDI, ORI, SLL, SRL • Data Transfer • LW, SW, LH, SH, LB, SB, LUI, MFHI, MFLO • Compare • SLT, SLTI • Control Flow • BEQ, BNE, J, JR, JAL

2. Basic Arithmetic Instructions • We already know about ADD and SUB instructions(R-Type). • ADD $TO,$T1,$T2 # $T0  $T1 + $T2 • SUB $S3,$S4,$S5 # $S3  $S4 - $S5 • The ADDI instruction (I-Type) is used to add a signed constant to the contents of a register. • ADDI $S1,$S2,100 # $S1  $S2 + 100 • ADDI $SP,$SP,-4 # $SP  $SP - 4

3. Compiling a Complex Assignment • Consider the following assignment from a C (or C++) program: • f = (g + h) – (i + j) • Keeping in mind that MIPS instructions can only perform a single operation at a time, what would a MIPS compiler produce? • Assume f, g, h, i, and j are associated with registers $s0, $s1, $s2, $s3, $s4. ADD $T0,$S3,$S4 # $T0  $S3 + $S4 ADD $T1,$S1,$S2 # $T1  $S1 + $S2 SUB $S0,$T1,$T0 # $S0  $T1 – $T0

4. Multiplication and Division • Multiplication (R-type) • MULT $S2,$S3 # Hi,Lo = $S2 * $S3 • MULTU $S2,$S3 # Hi,Lo = $S2 * $S3 (unsigned) • The 64-bit product is stored in two, 32-bit registers called Hi and Lo. Since there are no condition code flags in the MIPS processor, overflow is computed in software. • The Hi and Lo registers are accessed through special instructions (MFHI and MFLO) that move the contents of the Hi/Lo registers to a destination register, respectively. • Division (R-type) • DIV $S2,$S3 # Hi = remainder; Lo = quotient • DIVU $S2,$S3 # Hi = remainder; Lo = quotient • Overflow and divide-by-zero conditions must be computed in software.

5. Logical Instructions • AND (R-Type) • AND $S1,$S2,$S3 # $S1 = $S2 & $S3 • OR (R-Type) • OR $S1,$S2,$S3 # $S1 = $S2 | $S3 • NOR (R-Type) • NOR $S1,$S2,$S3 # $S1 = ~($S2 | $S3)

6. Logical Instructions (2) • ANDI (I-Type) • ANDI $S1,$S2,100 # $S1 = $S2 & 100 • The 16-bit constant is zero-extended. • ORI (I-Type) • ORI $S1,$S2,100 # $S1 = $S2 | 100 • The 16-bit constant is zero-extended.

7. Shift Instructions • Shift Left Logical (R-Type) • SLL $S1,$S2,16 # $S1 = $S2 << 16 • Vacated bits are filled with zeros. • Shift Right Logical (R-Type) • SRL $S1,$S2,23 # $S1 = $S2 >> 23 • Vacated bits are filled with zeros. 10110101011011100100011110101011 $S2 Before 01000111101010110000000000000000 $S1 After 10110101011011100100011110101011 $S2 Before 00000000000000000000000101101010 $S1 After

8. Data Transfer Instructions • The load word (LW) and store word (SW) instructions (I-Type) are used to transfer 32-bit words between the processor and memory. • Addresses are specified as an offset/base register pair. The address is formed by adding the constant offset (sign extended) to the contents of the base register. • LW $T1,32($T3) # $T1  Mem[$T3 + 32] • SW $T5,-16($SP) # Mem[$SP – 16]  $T5

9. Data Transfer Instructions (2) • Load and store half-word instructions (I-Type) are used to transfer 16-bit half words between the processor and memory. LH $T2,16($GP) # $T2[15..0]  Mem[$GP + 16] # The halfword is sign-extended SH $S4,-32($SP) # Mem[$SP–32]  $S4[15..0] • Load and store byte instructions (I-Type) are used to transfer 8-bit bytes between the processor and memory. LB $T2,-8($GP) # $T2[7..0]  Mem[$GP - 8] # The byte is sign-extended. SB $S4,24($SP) # Mem[$SP+24]  $S4[7..0]

10. Data Transfer Instructions (3) • The Load Upper Immediate (I-Type) instruction is used to initialize the upper 16 bits of a register with a constant. • Lower 16 bits of the register are set to zero. • LUI $S4, 255 # $S4[31..16] = 255; # $S4[15..0] = 0 • How can we use the LUI instruction to initialize a register with a 32-bit constant? • Example: Initialize $T3 with 0xFAFAFBFB. LUI $T3,0xFAFA # $T3 = 0xFAFA0000 ORI $T3,$T3,0xFBFB # ORI zero-extend the constant # $T3 = 0xFAFAFBFB

11. Data Transfer Instructions (4) • The MFHI and MFLO instruction (R-Type) are used to move the contents of the HI and LO registers to a destination register, respectively. • The HI and LO registers are set by the multiply and divide instructions. • MFHI $T5 # $T5  HI • MFLO $T2 # $T2  LO

12. Compiling an Assignment With a Memory Operand • Consider the following assignment: g = h + A[7]. • Assume g and h are stored in registers $S1 and $S2, and the starting (base) address of array A is stored in register $S3. • What will the compiler generate? LW $T0,28($S3) # $T0  Mem[$S3+28] ADD $S1,$S2,$T0 # $S1  $S2 + $T0 • Why is the offset = 28? • Memory is byte-addressable, but is organized as 32-bit words. That is why the offset = 7 × 4 = 28. • All memory addresses (of word-sized data) must be word aligned (multiple of 4).

13. More Memory Assignments • Assuming variable h is stored in register $S2 and the base address of array A is in $S3, what is the MIPS assembly code for the following assignment: A[12] = h + A[8]? LW $T0,32($S3) # $T0  Mem[$S3+32] ADD $T0,$S2,$T0 # $T0  $S2 + $T0 SW $T0,48($S3) # Mem[$S3+48]  $T0

14. Using a Variable Index Array • Assuming variables g, h, and i are associated with registers $S1, $S2, and $S4, respectively, and that the base address for array A is stored in register $S3, what is the MIPS assembly code for the following assignment: g = h + A[i]? ADD $T1,$S4,$S4 # $T1 = 2 * i ADD $T1,$T1,$T1 # $T1 = 4 * i ADD $T1,$T1,$S3 # $T1 = 4*i + $S3 LW $T0,0($T1) # $T0 = A[i] ADD $S1,$S2,$T0 # g = h + A[i]

15. Control-Flow Instructions • The MIPS instruction set includes a number of conditional and unconditional branch instructions for changing program control-flow. • Conditional branch instructions. • BEQ reg1,reg2,label # if reg1 == reg2, # goto label • BNE reg1,reg2,label # if reg1 != reg2, # goto label • Unconditional branch (jump) instructions. • J label # goto label • JR reg # goto address stored # in reg

16. Compiling if-then-else Statements • In the following C++ conditional statement, assume variables f, g, h, i, and j, are associated with registers $S0, $S1, $S2, $S3, and $S4, respectively. What is the corresponding assembly code? if (i == j) { f = g + h; } else { f = g – h; } BNE $S3,$S4,ELSE ADD $S0,$S1,$S2 J EXIT ELSE: SUB $S0,$S1,$S2 EXIT:

17. Compiling while Loops • In the following C++ while loop, assume variables i, j, and k are associated with registers $S3, $S4, and $S5, respectively; and that the base address of array SAVE is stored in register $S6. What is the corresponding assembly code? while (SAVE[i] == k) { i = i + j; } LOOP: ADD $T1,$S3,$S3 ADD $T1,$T1,$T1 ADD $T1,$T1,$S6 LW $T0,0($T1) BNE $T0,$S5,EXIT ADD $S3,$S3,$S4 J LOOP EXIT:

18. The Compare Instruction • The MIPS instruction set includes a compare instruction (R-Type) that is commonly used in conjunction with conditional branch instructions. • SLT $T0,$S3,$S4# if ($S3 < $S4) $T0 = 1 # else $T0 = 0 • The result (1 or 0) substitutes for a condition code flag. • A compare-immediate instruction (I-Type) is also part of the MIPS instruction set. • SLTI $T0,$S3,68 # if ($S3 < 68) $T0 = 1 # else $T0 = 0 • Since comparisons are frequently made with the number zero, register $ZEROis commonly used for this purpose.

19. Compiling if-then-else Statements (2) • If variables a, b, f, g and h are associated with registers $S0, $S1, $S2, $S3 and $S4, respectively, what is the assembly code that gets generated for the following C++ statement: if (a < b) { f = g + h; } else { f = g – h; } SLT $T0,$S0,$S1 BEQ $T0,$ZERO,ELSE ADD $S2,$S3,$S4 J EXIT ELSE: SUB $S2,$S3,$S4 EXIT: