IP - Brno

1. IP - Brno June 2004 Design Solutions with Programmable Logic Devices and VHDL by Ing. Jeroen Lambert

2. Overview • Design Requests • Electronic Design - Now and Then • Technology Overview • VHDL • Solutions • Simulation • Implementation

3. Design Requests • VME bus interface • Precise DC Motorcontroller

4. Electronic Design - Now & Then • Previously: • PCB design - components • digital design - logic comp • Now: • PCB design - components • digital design - programmable Hardware Only Hardware&Syntax(software)

5. Overview • Design Requests • Electronic Design - Now and Then • PLD solution - Technology Overview • VHDL • Solutions • Simulation • Implementation

6. Technology Overview • Programmable Logic • What? • PLD principle • Devices available today • Manufacturers

7. What is programmable logic? • A device with configurable combinatorial logic and flip-flops linked together with programmable resources that control the interconnections • Differences between all types: • Number of gates • One time programmable / re-programmable • ‘In-system programmable’ / ‘out of system programmable’ • Switch technology • Architecture (based on combinatorial logic and FF’s)

8. CMOS Logic Standard ASIC uProcessors Programmable Logic Logic uControllers What is programmable logic?

9. Overview • Programmable Logic • What? • PLD principle • Devices available today • Manufacturers

10. B A _ A _ B AND array B A _ _ A B _ _ A B _ A B _ A B product lines _ A B _ A B A B A B input lines fuses OR array Q1 Q2 Q3 Q4 Sum of product outputs PLD principle • Before programming:

11. B A _ A AND array _ B A B _ _ A B _ _ A B _ A B _ A B product lines _ A B _ A B A B A B input lines fuses OR array Q1 Q2 Q3 Q4 Sum of product outputs PLD principle • PLD after programming the predefined functions:

12. Overview • Programmable Logic • What? • PLD principle • Devices available today • Manufacturers

13. CMOS Logic ASIC uProcessors Programmable Standard Logic Logic uControllers SPLD CPLD FPGA Programmable logic devices available today • Major programmable logic architecture:

14. SPLD - simple programmable logic device • Also known as: • PAL (Programmable Array Logic) • PLA (Programmable Logic Array) • GAL (Generic Array Logic) • Features: • smallest • fastest • least-expensive • use fuses or non-volatile memory cells like EPROM, E2PROM, FLASH • Density • 4 - 200 gates • replacement for a certain amount of 7400 series devices

15. D C B A OR plane AND plane O3 O2 O1 O0 SPLD - simple programmable logic device • PAL architecture • 2 levels of logic gates: • AND plane: • programmable • contains product terms • OR plane: • hard-wired • contains sum of product terms • Before programming:

16. D C B A OR plane A.B C’.D’ 0 0 A.B’.C 0 0 0 A.B.C’.D’ A’.B’.C.D 0 0 A B.D’ C.D’ 0 AND plane O3 O2 O1 O0 SPLD - simple programmable logic device • PAL programmed for given functions

17. D C B A OR plane AND plane O3 O2 O1 O0 SPLD - simple programmable logic device • PLA architecture • 2 levels of logic gates: • AND plane: • programmable • contains product terms • OR plane: • programmable • contains sum of the product terms

18. SPLD - simple programmable logic device • GAL architecture • 2 levels of logic gates: • AND plane: • programmable • contains product terms • OR array: • hard-wired with FFs • contains sum of the product terms

19. CPLD - complex programmable logic device • Many families of different vendors: • EPLD (Erasable Programmable Logic Device) • EEPLD (Electrically-Erasable Programmable Logic Device) • 9500 CPLD Family from Xilinx • MAX (Multiple Array matriX) from Altera • …. • Use non-volatile memory cells such as EPROM, E2PROM and FLASH • Used to implement complex subsystems like UARTs, digital filters, etc.

20. CPLD - complex programmable logic device • Higher capacity: • Typical CPLD: • equivalent with 2 to 64 SPLDs • contains 10s to few hundred macrocells • 8 to 16 macrocells (usually fully connected) grouped together in larger function block • multiple function bocks mostly further interconnected (depends on vendor and family) • Higher density: • 150 to 45 000 gates or more • replace dozens to hundreds of 74XX series devices

21. CPLD - complex programmable logic device

22. CPLD - complex programmable logic device • Major variations between CPLD architectures: • number of product terms per macrocell • borrow or allocate product terms • number of connections in the switch matrix • all possible connections are supported (fully - populated) • delays are generally fixed and predictable • no problems by routing your design • not all possible connections are supported (partially - populated) • delays are not fixed and less easily predicted • less expensive to manufacture • can give problems by routing a complex design

23. FPGA - Field Programmable Gate Array • Consists of: • array of uncommitted logic blocks • interconnect resources • surrounded by programmable IO-blocks • Highest logic capacity: • thousands to millions of gates • thousands CLBs (Configurable Logic Block)

24. FPGA - Field Programmable Gate Array • Architecture of FPGA:

25. FPGA - Field Programmable Gate Array • Structure of a configurable logic block (CLB):

26. FPGA - Field Programmable Gate Array • Structure of a programmable interconnect:

27. FPGA - Field Programmable Gate Array • CLBs are not 100% interconnected • Logic is placed through software like PCB autorouter • Secret to density and performance: • logic in CLBs • efficiency of routing architecture

28. FPGA - Field Programmable Gate Array • Two primary classes of FPGA architectures: • coarse-grained: • fairly large logic blocks • 2 or more 4 input LUTs • 2 or more FFs • tine-grained: • large number of relatively simple logic blocks • 2 inputs logic function or a 4-to-1 multiplexer • a flip-flop

29. Number of gates in PLDs

30. FPGA - Market Example Xilinx - Virtex II Altera - Stratix II

31. CMOS Logic ASIC uProcessors Programmable Standard Logic Logic uControllers SPLD CPLD FPGA Programmable logic devices - ASIC

32. ASIC - Application-Specific Integrated Circuit • Analog / Digital / MIX • Features: • customized to a specific task • not flexible • low production cost, high design cost • only for large production • possibility of migration from PLDs and FPGAs, HDL description can be used to specify the ASIC structure (personalization)

33. Overview • What is programmable logic? • PLD principle • Programmable logic devices available today • Overview of manufacturers

34. Overview of manufacturers

35. CMOS Logic Standard ASIC uProcessors Programmable Logic Logic uControllers Evolution Nios embedded processor IBM power pc embedded processor

36. Overview • Design Requests • Electronic Design - Now and Then • Technology Overview • VHDL • Solutions • Simulation • Implementation

37. Overview • What is VHDL, Applications, Benefits and Design Flow? • VHDL language and syntax • General • Structure of a .VHD file • Concurrent & Sequential Statements • Synchronous logic & State machines

38. What is VHDL • VHDL = double acronym • VHDL = VHSIC Hardware Description Language • VHSIC = Very High Speed Integrated Circuit • Developed in the early 80s by the American Department of Defense • Defined by international standards • IEEE Std 1076 – 1987 • IEEE Std 1076 – 1993

39. Application area • Describe architecture and behavior of discrete electronic systems • Modeling System Hardware • Embedded systems: co-design & co-verification • Hardware Implementation: CPLD, FPGA, ...

40. Benefits of Using VHDL • Design at higher level • very powerful language constructs • locate problems in early stage • Device independent • use same code for different target devices • choice of tools & vendors • Flexibility • IP re-use: libraries & components • Top-down philosophy • large projects with different teams of designers • functional simulation of building blocks • Quick time-to-market and low cost

41. Limitations/drawbacks • Only digital system design • The VHDL code may not always describe an optimal function • Not always most effective use of resources

42. f Abstraction levels Behavioural RTL Logic Layout

43. Abstraction levels (Cont’d) • Behaviour level: • functional description of the model • no system clock • simulatable, not synthesizable • to create stimuli • RT (Register Transfer) level: • combinatorial logic and storage elements • system clock • simulatable and synthesizable • Logic level: • interconnect of logic gates and storage elements • detailed timing • Layout: • detailed timing

44. Design flow VHDL editor Behavioural Device independent optimisation RTL Device fitting or Place & Route Software Logic Device dependent Layout

45. Design entry Simulation no Results OK? yes Synthesis/optimisation no Results OK? yes Timing analysis and layout Top-down design philosophy • Allows: • early testing • easy change of technology • structured system design

46. Overview • What is VHDL, Applications, Benefits and Design Flow? • VHDL language and syntax • General • Structure of a .VHD file • Concurrent & Sequential Statements • Synchronous logic & State machines

47. General • Case insensitive • VHDL keyword: lower case letters • self defined identifiers: upper case letters • Sequential statements • executed one after another • functions, procedures • Concurrent statements • executed in parallel • instantiation

48. bit Process Process Std_logic integer my _type bit _vector (0 to 3) Process Process General (Cont’d) • Signal types: • each signal has a type • VHDL provides predefined types • bit • bit_vector • integer • …. • user can define his own types • makes the code more readable • useful in state machines

49. Overview • What is VHDL, Applications, Benefits and Design Flow? • VHDL language and syntax • General • Structure of a .VHD file • Concurrent & Sequential Statements • Synchronous logic & State machines

50. Entity • Describes the interface or black box • No behavioral description entity HALFADD is port(A : in std_logic; B : in std_logic; SUM, CARRY : out std_logic ); end HALFADD; A SUM B CARRY