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Review

Review. We would like to have the capacity of disk at the speed of the processor: unfortunately this is not feasible. So we create a memory hierarchy: each successively lower level contains “most used” data from next higher level exploits temporal locality

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Review

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  1. Review • We would like to have the capacity of disk at the speed of the processor: unfortunately this is not feasible. • So we create a memory hierarchy: • each successively lower level contains “most used” data from next higher level • exploits temporal locality • do the common case fast, worry less about the exceptions (design principle of MIPS) • Locality of reference is a Big Idea

  2. Outline • Block Size Tradeoff • Types of Cache Misses • Fully Associative Cache • N-Way Associative Cache • Block Replacement Policy • Multilevel Caches • Cache write policy

  3. Block Size Tradeoff (1/3) • Benefits of Larger Block Size • Spatial Locality: if we access a given word, we’re likely to access other nearby words soon • Very applicable with Stored-Program Concept: if we execute a given instruction, it’s likely that we’ll execute the next few as well • Works nicely in sequential array accesses too

  4. Block Size Tradeoff (2/3) • Drawbacks of Larger Block Size • Larger block size means larger miss penalty • on a miss, takes longer time to load a new block from next level • If block size is too big relative to cache size, then there are too few blocks • Result: miss rate goes up • In general, minimize Average Access Time = Hit Time x Hit Rate + Miss Penalty x Miss Rate

  5. Block Size Tradeoff (3/3) • Hit Time = time to find and retrieve data from current level cache • Miss Penalty = average time to retrieve data on a current level miss (includes the possibility of misses on successive levels of memory hierarchy) • Hit Rate = % of requests that are found in current level cache • Miss Rate = 1 - Hit Rate

  6. Valid Bit Cache Data Tag B 3 B 2 B 1 B 0 Extreme Example: One Big Block • Cache Size = 4 bytes Block Size = 4 bytes • Only ONE entry in the cache! • If item accessed, likely accessed again soon • But unlikely will be accessed again immediately! • The next access will likely to be a miss again • Continually loading data into the cache butdiscard data (force out) before use it again • Nightmare for cache designer: Ping Pong Effect

  7. Miss Rate Miss Penalty Exploits Spatial Locality Fewer blocks: compromises temporal locality Block Size Block Size Average Access Time Increased Miss Penalty & Miss Rate Block Size Block Size Tradeoff Conclusions

  8. Types of Cache Misses (1/2) • Compulsory Misses • occur when a program is first started • cache does not contain any of that program’s data yet, so misses are bound to occur • can’t be avoided easily, so won’t focus on these in this course

  9. Types of Cache Misses (2/2) • Conflict Misses • miss that occurs because two distinct memory addresses map to the same cache location • two blocks (which happen to map to the same location) can keep overwriting each other • big problem in direct-mapped caches • how do we lessen the effect of these?

  10. Dealing with Conflict Misses • Solution 1: Make the cache size bigger • fails at some point • Solution 2: Multiple distinct blocks can fit in the same Cache Index?

  11. Fully Associative Cache (1/3) • Memory address fields: • Tag: same as before • Offset: same as before • Index: non-existent • What does this mean? • no “rows”: any block can go anywhere in the cache • must compare with all tags in entire cache to see if data is there

  12. 4 31 0 Byte Offset Cache Tag (27 bits long) Cache Data Valid Cache Tag : B 0 B 31 B 1 = = = = : : : : = Fully Associative Cache (2/3) • Fully Associative Cache (e.g., 32 B block) • compare tags in parallel

  13. Fully Associative Cache (3/3) • Benefit of Fully Assoc Cache • no Conflict Misses (since data can go anywhere) • Drawbacks of Fully Assoc Cache • need hardware comparator for every single entry: if we have a 64KB of data in cache with 4B entries, we need 16K comparators: infeasible

  14. Third Type of Cache Miss • Capacity Misses • miss that occurs because the cache has a limited size • miss that would not occur if we increase the size of the cache • sketchy definition, so just get the general idea • This is the primary type of miss for Fully Associative caches.

  15. N-Way Set Associative Cache (1/4) • Memory address fields: • Tag: same as before • Offset: same as before • Index: points us to the correct “row” (called a set in this case) • So what’s the difference? • each set contains multiple blocks • once we’ve found correct set, must compare with all tags in that set to find our data

  16. N-Way Set Associative Cache (2/4) • Summary: • cache is direct-mapped with respect to sets • each set is fully associative • basically N direct-mapped caches working in parallel: each has its own valid bit and data

  17. Cache Index Valid Cache Tag Cache Data Cache Data Cache Tag Valid Cache Block 0 Cache Block 0 : : : : : : Adr Tag Compare Compare 1 0 Mux Sel1 Sel0 OR Cache Block Hit Two-way Set Associative Cache

  18. N-Way Set Associative Cache (3/4) • Given memory address: • Find correct set using Index value. • Compare Tag with all Tag values in the determined set. • If a match occurs, it’s a hit, otherwise a miss. • Finally, use the offset field as usual to find the desired data within the desired block.

  19. N-Way Set Associative Cache (4/4) • What’s so great about this? • even a 2-way set assoc cache avoids a lot of conflict misses • hardware cost isn’t that bad: only need N comparators • In fact, for a cache with M blocks, • it’s Direct-Mapped if it’s 1-way set assoc • it’s Fully Assoc if it’s M-way set assoc • so these two are just special cases of the more general set associative desgin

  20. 4 Byte Direct Mapped Cache Cache Index Memory Address Memory 0 0 1 1 2 2 3 3 4 5 6 7 8 9 A B C D E F Associative Cache Example • Recall this is how a simple direct mapped cache looked.

  21. Cache Index Memory Address Memory 0 0 0 1 1 2 1 3 4 5 6 7 8 9 A B C D E F Associative Cache Example • Here’s a simple 2 way set associative cache.

  22. Block Replacement Policy (1/2) • Direct-Mapped Cache: index completely specifies position which position a block can go in on a miss • N-Way Set Assoc (N > 1): index specifies a set, but block can occupy any position within the set on a miss • Fully Associative: block can be written into any position • Question: if we have the choice, where should we write an incoming block?

  23. Block Replacement Policy (2/2) • Solution: • If there are any locations with valid bit off (empty), then usually write the new block into the first one. • If all possible locations already have a valid block, we must pick a replacement policy: rule by which we determine which block gets “cached out” on a miss.

  24. Block Replacement Policy: LRU • LRU (Least Recently Used) • Idea: cache out block which has been accessed (read or write) least recently • Pro: temporal locality => recent past use implies likely future use: in fact, this is a very effective policy • Con: with 2-way set assoc, easy to keep track (one LRU bit); with 4-way or greater, requires complicated hardware and much time to keep track of this

  25. Block Replacement Example • We have a 2-way set associative cache with a four word total capacity and one word blocks. We perform the following word accesses (ignore bytes for this problem): 0, 2, 0, 1, 4, 0, 2, 3, 5, 4 How many hits and how many misses will there be for the LRU block replacement policy?

  26. set 0 set 1 set 0 0 set 1 set 0 0 2 set 1 lru set 0 0 2 set 1 set 0 0 lru set 1 1 set 0 0 4 lru set 1 1 Block Replacement Example: LRU loc 0 loc 1 lru 0 • 0: miss, bring into set 0 (loc 0) • Addresses 0, 2, 0, 1, 4, 0, ... lru 2 • 2: miss, bring into set 0 (loc 1) lru • 0: hit • 1: miss, bring into set 1 (loc 0) lru 1 lru 4 • 4: miss, bring into set 0 (loc 1, replace 2) lru • 0: hit

  27. Ways to reduce miss rate • Larger cache • limited by cost and technology • hit time of first level cache < cycle time • More places in the cache to put each block of memory - associativity • fully-associative • any block any line • k-way set associated • k places for each block • direct map: k=1

  28. Big Idea • How chose between options of associativity, block size, replacement policy? • Design against a performance model • Minimize: Average Access Time = Hit Time + Miss Penalty x Miss Rate • influenced by technology and program behavior • Create the illusion of a memory that is large, cheap, and fast - on average

  29. Example • Assume • Hit Time = 1 cycle • Miss rate = 5% • Miss penalty = 20 cycles • Avg mem access time = 1 + 0.05 x 20 = 2 cycle

  30. DRAM $ $2 Improving Miss Penalty • When caches first became popular, Miss Penalty ~ 10 processor clock cycles • Today 1000 MHz Processor (1 ns per clock cycle) and 100 ns to go to DRAM  100 processor clock cycles! MEM Proc Solution: another cache between memory and the processor cache: Second Level (L2) Cache

  31. L2 hit time L2 Miss Rate L2 Miss Penalty Analyzing Multi-level cache hierarchy DRAM Proc $ $2 L1 hit time L1 Miss Rate L1 Miss Penalty Avg Mem Access Time = L1 Hit Time + L1 Miss Rate * L1 Miss Penalty L1 Miss Penalty = L2 Hit Time + L2 Miss Rate * L2 Miss Penalty Avg Mem Access Time = L1 Hit Time + L1 Miss Rate * (L2 Hit Time + L2 Miss Rate * L2 Miss Penalty)

  32. Typical Scale • L1 • size: tens of KB • hit time: complete in one clock cycle • miss rates: 1-5% • L2: • size: hundreds of KB • hit time: few clock cycles • miss rates: 10-20% • L2 miss rate is fraction of L1 misses that also miss in L2 • why so high?

  33. Example (cont) • Assume • L1 Hit Time = 1 cycle • L1 Miss rate = 5% • L2 Hit Time = 5 cycles • L2 Miss rate = 15% (% L1 misses that miss) • L2 Miss Penalty = 100 cycles • L1 miss penalty = 5 + 0.15 * 100 = 20 • Avg mem access time = 1 + 0.05 x 20 = 2 cycle

  34. Example: without L2 cache • Assume • L1 Hit Time = 1 cycle • L1 Miss rate = 5% • L1 Miss Penalty = 100 cycles • Avg mem access time = 1 + 0.05 x 100 = 6 cycles • 3x faster with L2 cache

  35. Set Associative or Fully Associative: • Random • LRU (Least Recently Used) Associatively: 2-way 4-way 8-way Size lru vs random 16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0% 64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5% 256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%

  36. What to do on a write hit? • Write-through • update the word in cache block and corresponding word in memory • Write-back • update word in cache block • allow memory word to be “stale” => add ‘dirty’ bit to each line indicating that memory needs to be updated when block is replaced => OS flushes cache before I/O !!! • Performance trade-offs?

  37. Write Buffer for Write Through • Processor: writes data into the cache and the write buffer • Memory controller: write contents of the buffer to memory • Works fine if: Store frequency (w.r.t. time) << 1 / DRAM write cycle • Memory system designer’s nightmare: • Store frequency (w.r.t. time) -> 1 / DRAM write cycle • Write buffer saturation Cache Processor DRAM Write Buffer

  38. Things to Remember (1/2) • Caches are NOT mandatory: • Processor performs arithmetic • Memory stores data • Caches simply make data transfers go faster • Each level of memory hierarchy is just a subset of next higher level • Caches speed up due to temporal locality: store data used recently • Block size > 1 word speeds up due to spatial locality: store words adjacent to the ones used recently

  39. Things to Remember (2/2) • Cache design choices: • size of cache: speed v. capacity • direct-mapped v. associative • for N-way set assoc: choice of N • block replacement policy • 2nd level cache? • Write through v. write back? • Use performance model to pick between choices, depending on programs, technology, budget, ...

  40. The Art of Memory System Design Workload or Benchmark programs Processor reference stream <op,addr>, <op,addr>,<op,addr>,<op,addr>, . . . op: i-fetch, read, write Memory Optimize the memory system organization to minimize the average memory access time for typical workloads $ MEM

  41. 1 KB Direct Mapped Cache with 32 B Blocks • For a 2 ** N byte cache: • The uppermost (32 - N) bits are always the Cache Tag • The lowest M bits are the Byte Select (Block Size = 2 ** M) 31 9 4 0 Cache Tag Example: 0x50 Cache Index Byte Select Ex: 0x01 Ex: 0x00 Stored as part of the cache “state” Valid Bit Cache Tag Cache Data : Byte 31 Byte 1 Byte 0 0 : 0x50 Byte 63 Byte 33 Byte 32 1 2 3 : : : : Byte 1023 Byte 992 31

  42. Cache Data Cache Tag Valid Cache Block 0 : : : Compare A Two-way Set Associative Cache • N-way set associative: N entries for each Cache Index • N direct mapped caches operates in parallel • Example: Two-way set associative cache • Cache Index selects a “set” from the cache • The two tags in the set are compared in parallel • Data is selected based on the tag result Cache Index Valid Cache Tag Cache Data Cache Block 0 : : : Adr Tag Compare 1 0 Mux Sel1 Sel0 OR Cache Block Hit

  43. Cache Index Valid Cache Tag Cache Data Cache Data Cache Tag Valid Cache Block 0 Cache Block 0 : : : : : : Adr Tag Compare Compare 1 0 Mux Sel1 Sel0 OR Cache Block Hit Disadvantage of Set Associative Cache • N-way Set Associative Cache versus Direct Mapped Cache: • N comparators vs. 1 • Extra MUX delay for the data • Data comes AFTER Hit/Miss decision and set selection • In a direct mapped cache, Cache Block is available BEFORE Hit/Miss: • Possible to assume a hit and continue. Recover later if miss.

  44. A Summary on Sources of Cache Misses • Compulsory (cold start or process migration, first reference): first access to a block • “Cold” fact of life: not a whole lot you can do about it • Note: If you are going to run “billions” of instruction, Compulsory Misses are insignificant • Conflict (collision): • Multiple memory locations mappedto the same increase associativity • Capacity: • Cache cannot contain all blocks access by the program • Solution: increase cache size • Invalidation: other process (e.g., I/O) updates memory

  45. Source of Cache Misses Quiz Direct Mapped N-way Set Associative Fully Associative Cache Size: Small, Medium, Big? Compulsory Miss: Conflict Miss Capacity Miss Invalidation Miss Choices: Zero, Low, Medium, High, Same

  46. Improving Cache Performance: 3 general options 1. Reduce the miss rate, 2. Reduce the miss penalty, or 3. Reduce the time to hit in the cache.

  47. 4 Questions for Memory Hierarchy • Q1: Where can a block be placed in the upper level? (Block placement) • Q2: How is a block found if it is in the upper level? (Block identification) • Q3: Which block should be replaced on a miss? (Block replacement) • Q4: What happens on a write? (Write strategy)

  48. Q4: What happens on a write? • Write through—The information is written to both the block in the cache and to the block in the lower-level memory. • Write back—The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. • is block clean or dirty? • Pros and Cons of each? • WT: read misses cannot result in writes • WB: no writes of repeated writes • WT always combined with write buffers so that don’t wait for lower level memory

  49. Write Buffer for Write Through • A Write Buffer is needed between the Cache and Memory • Processor: writes data into the cache and the write buffer • Memory controller: write contents of the buffer to memory • Write buffer is just a FIFO: • Typical number of entries: 4 • Works fine if: Store frequency (w.r.t. time) << 1 / DRAM write cycle • Memory system designer’s nightmare: • Store frequency (w.r.t. time) -> 1 / DRAM write cycle • Write buffer saturation Cache Processor DRAM Write Buffer

  50. Write Allocate versus Not Allocate • Assume: a 16-bit write to memory location 0x0 and causes a miss • Do we read in the block? • Yes: Write Allocate • No: Write Not Allocate 31 9 4 0 Cache Tag Example: 0x00 Cache Index Byte Select Ex: 0x00 Ex: 0x00 Valid Bit Cache Tag Cache Data : 0x00 Byte 31 Byte 1 Byte 0 0 : Byte 63 Byte 33 Byte 32 1 2 3 : : : : Byte 1023 Byte 992 31

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