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Digital Printing R&D 5 group

Education of Iris (CLX-3160(F)N). Digital Printing R&D 5 group. AUGUST , 2006. Agenda. Outline Composition & Function Schematic Trouble shooting. Ⅰ.Outline. Objectives. Understanding the basic structures and function of Hardware Checking & building ability to Trouble Shooting.

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Digital Printing R&D 5 group

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  1. Education of Iris (CLX-3160(F)N) Digital Printing R&D 5 group AUGUST, 2006

  2. Agenda • Outline • Composition & Function • Schematic • Trouble shooting

  3. Ⅰ.Outline Objectives • Understanding the basic structures and function of Hardware • Checking & building ability to Trouble Shooting

  4. Ⅱ. Composition & Function System Configuration

  5. Ⅱ. Composition & Function Block Diagram of CLX-3160 Series

  6. Ⅱ. Composition & Function H/W Configuration (Engine & Controller) HVPS SMPS Main Board

  7. Ⅱ. Composition & Function H/W Configuration (SCAN & Pannel) ADF Flatten Joint USB Host Joint Pannel

  8. Ⅱ. Composition & Function Main B’D Configuration Engine Control Mechanical Part Electrical Part (Motor & Actuator) (HVPS & Sensors) I/O & PWM Port DATA (31:0) SD_DATA (31:0) FLASH SDRAM ADDR (31:0) ROM SD_ADDR (31:0) USB Device Host Phy MII Chip 3.3V I2C BUS LDO NVRAM 1.2V Switching Panel & SCF Control Scan interface Regulator UART CLX-3160 Series Main B’D ADF & Flatten CCDM SCAN MODULE

  9. Ⅱ. Composition & Function Main B’D Configuration (Con’t) CPU : Chorus M (SoC) Memory : - RAM : 128MB SDRAM - ROM : 4MB FLASH - NVRAM : 8KB (4K : N/W Parameter (MAC Address)) Peripherals : - USB 2.0 - USB Host (PictBridge, SCAN to USB, USB to Print…) - 10/100 Based N/W (MII Interface Phy Chip Used) I/O : - Digital I/O Port : Basic I/O, PWM : Motor & HVPS Control - UART : SCF & Panel Communication, Debug - I2C : NVRAM & CRUM Interface (EEPROM : 24C64, 34C02) - Analog I/O Port (ADC : Sensor Interface, DAC : LD Power Control)

  10. Ⅱ. Composition & Function Chorus M Architecture CPU Core : ARM920 T 300Mhz (I-Cache : 16KB, D-Cache : 16KB) SDRAM Controller : 5 Bank, 100Mhz System Bus ROM Controller : 4 Banks ( 2 Bank Used) NAND FLASH Controller : 8/16 Bits interface (Not used) I/O Controller : 6 Banks DMA Controller : 6 Channel HPVC : Dual / Single Beam PVC : Dual / Single Beam (Not Used ) UART : 5 Channels (Debug 1 Channel used only) Interrupt : 6 External, 26 Internal TIMER : 6 System Timer (S/W use Only)

  11. Ⅱ. Composition & Function Memory Interface ROM : - 4MB Nor Flash used - Interface With Chorus M ROM Controller RAM : - 128MB SDRAM - Interface with Chorus M RAM Controller NVRAM : - Size : 8KB - Interface With Chorus M I2C Controller CRUM : - Size : 256B - Interface With Chorus M I2C Controller via Deve Joint B’D

  12. Ⅱ. Composition & Function I/O Interface USB - High Speed USB 2.0 Device - USB Host (PictBridge) N/W Embedded - Chorus M With MII Interface FAX - Smart DAA PWM - High Voltage Control With Duty - Main Motor Clock I2C Interface - NVRAM - CRUM

  13. Ⅱ. Composition & Function Power Flow SMPS - Type III (Standard) - +24V : For use Mechanical Part (Motor & Actuator (Solenoid, Clutch)) - +5V : Logic, Analog, Sensor, Main B’D - Supply From SMPS +5V - Power Supply with two Regulator (3.3V : LDO, 1.2V : Switching Regulator) - 3.3V : I/O Operating (Digital & Analog) - 1.2V : Chorus M Core Voltage HVPS - High Voltage Source for EP Condition - Supply From SMPS +24V - Controlled By PWM Pulse & I/O

  14. Ⅱ. Composition & Function CRUM Interface

  15. Ⅲ. Schematic Chorus M (1)

  16. Ⅲ. Schematic Chorus M (2)

  17. Ⅲ. Schematic Power & Clock Regulator : 3.3V & 1.2V Clock Source - Main : 12Mhz - Video : 12Mhz

  18. Ⅲ. Schematic Flash Memory Flash Memory Size

  19. Ⅲ. Schematic SDRAM SDRAM Size

  20. Ⅲ. Schematic USB Interface USB 2.0 High Speed Clock Source : 12Mhz USB 1.1 Clock Source : 6Mhz

  21. Ⅲ. Schematic Embedded Network Embedded N/W (10/100M) Green LED : Activity Orange LED : Link

  22. Ⅲ. Schematic CCDM & ADF Analog Front-End(ADC) Shading Memory CCFL Control by PWM

  23. Ⅲ. Schematic I2C & Panel Interface *I2C Address *

  24. Ⅲ. Schematic LSU Interface Motor Control Signal - Clock, Enable, Ready LD Beam Control - Video, S/H, Hsync

  25. Ⅲ. Schematic Sensor & Fuser Circuit Sensor : Photo Interrupt Fuser : Linearization & Protection SCF : Simple Asyn Serial Communication

  26. Ⅲ. Schematic Actuator Driving & Interface Circuit

  27. Ⅲ. Schematic SMPS & HVPS Interface , Interlock S/W

  28. Ⅲ. Schematic SMPS

  29. Ⅲ. Schematic HVPS (Charger)

  30. Ⅲ. Schematic HVPS (Supply)

  31. Ⅲ. Schematic HVPS (Intermediate Transfer & Reference Voltage)

  32. Ⅲ. Schematic HVPS (Transfer)

  33. Ⅲ. Schematic HVPS (Developer High Voltage Switch)

  34. Ⅲ. Schematic SCF B’D (CPU)

  35. Ⅲ. Schematic SCF B’D (Memory & Motor Controller)

  36. Ⅲ. Schematic SCF B’D (Sensor & Actuator Driver)

  37. Ⅲ. Schematic Panel B’D

  38. Ⅲ. Schematic Flatten Joint B’D

  39. Ⅲ. Schematic ADF B’D

  40. Ⅱ. Common Installer Dialog Details Ⅴ. Trouble shooting Objectives • To give some solutions with trouble

  41. Ⅴ. Trouble shooting No Power (1)

  42. Ⅴ. Trouble shooting No Power (2)

  43. Ⅴ. Trouble shooting LSU error

  44. Ⅴ. Trouble shooting Fuser error

  45. Ⅴ. Trouble shooting Toner error

  46. Ⅴ. Trouble shooting Scanner Locked

  47. Ⅴ. Trouble shooting Copying & Scanning error

  48. Ⅵ. Review Review Ⅰ. Do you have any question for troubleshooting? Ⅱ. Is there anything to request for better service?

  49. Thank you!!!

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