EMT 511/3 DIGITAL SYSTEM DESIGN

1. By: Dr. Mohd Nazrin Md IsaBlock 7, Ground Floor, School of Microelectronic Engineering, Universiti Malaysia Perlis. nazrin.unimap.edu.my EMT 511/3 DIGITAL SYSTEM DESIGN

2. COURSE Introduction

3. Course Outcomes • CO1: Ability to discover and apply computer-aided design tools for design of complex digital logic circuits. • CO2: Ability to design, analyze, synthesize and evaluate complex digital circuits. • CO3: Ability to apply and design with programmable logic.

4. Specific Outcomes After completing this course, you will be able to: • Understand ALTERA FPGA design flow • Identify basic design guidelines for a successful chip design • Differentiate a synthesizable and non- synthesizable HDL designs • Select a proper HDL coding style for fast, efficient digital circuits

5. Delivery and Assessments • Assignment 1 (20%): • (a)Latch Inference and effects (Individual) • Incomplete if-else statement • Incomplete case statement • Incomplete sensitivity list elements • (b) Blocking vs non-blocking signal assignment • Assignment 2 (20%): Modular HDL design (Individual) • Temperature monitoring and controlling system using FPGA Results: resource utilizations, logic levels, critical path, operating frequency. • Design Project (20%): Pipelined Multiplier using SA (group of 2). • Report format: One 4-page IEEE paper • Results (as above) • In-class Exercises/ Discussions • 1 : Switches and LEDs • RTL coding • Test bench writing • Behavioral Simulation • 2: Binary to Hex Decoder • RTL coding with bugs • HDL debugging • 3: Boiler Control System • 4: Traffic light controller • 5: Multiplier

6. Text books

7. ACADEMIC CALENDAR (PART 1)

8. Introduction

9. Contents • Introduction • FPGA Design Flow • HDL Design For Synthesis • Review of Verilog modeling structure • Review of Verilog data types • Review of Verilog operators • Review of behavioral modeling • Coding for performance tips and tricks • Review of Test bench

10. C/C++ vs HDL

11. C/C++ vs HDL (cont’d)

12. VHDL vs Verilog

13. FPGA Design Flow

14. BASIC FPGA DESIGN FLOW Andgate.v Andgate_tb.v Andgate.sof

15. DE2-115 Board Information

16. DE2-115 Board Information (cont’d)

17. The DE2-115 Block Diagram Labs: slide switches, push buttons, Seven Segment displays

18. Quartus II

19. HDL Synthesis

20. Pin Planner

21. Simulation (using ALTERA Modelsim) Requires a test bench file (another Verilog module)

22. Configuring bit stream (.sof) FPGA in JTAG Mode Ensure that power is applied to the DE2-115 board Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the RUN position Connect the supplied USB cable to the USB Blaster port on the DE2-115 board The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the .sof filename extension SOF = SRAM Object File

23. Configuring bit stream (.pof) FPGA in AS Mode

24. HDL Design for Synthesis

25. Importance of HDL • Designs can be described at very abstract level using HDL • can write without sticking to any technology • Functional verification can be done early in the design cycle • can optimize & modify RTL description until meet desired functionality • Tools: E.g:VCS (Verilog Compiled Simulator), Modelsim • HDL design is analogous to computer programming • provide concise representation of design compared to schematic

26. Simulation At Different Levels • RTL • Design represented by Verilog/VHDL RTL code • High simulation performance • Primary method to debug functional problems • Gate • Design represented as a netlist • Netlist generated by implementation tools (synthesis, P&R) • Slow simulation speed • Circuit • Design represented as SPICE netlist • Highest level of accuracy but slowest simulation speed • Used mainly for critical paths, analog circuits and cell characterization

27. Levels of Abstraction

28. Verilog Modeling Structure

29. Modules – What’s Inside? module name port list, port declaration (if port presents) parameters (optional) declaration of wires, regs & other variables data flow statements (assign) instantiation of lower modules always & initial blocks all behavioral statements in these blocks tasks & functions endmodule statement

30. Modules - Format • module <module_name> (<module_terminal_list>) • <direction_of_terminals> • … • <module_internals> • … • endmodule E.g. For a D flip-flop, named DFF, with data, clock as 1-bit inputs, & q as output terminal, the module will be defined as: • module DFF (data, clock, q); • input data, clock; • output q; • … • <the function of D flip-flop> • … • endmodule How to describe the terminals with more than 1-bit?

31. Hierarchical/Modular Design Example Test_Tb.v Test bench Top.v Top Most Design Unit A.v B.V Sub-Blocks (cells) A B C C.v Each unit is coded in a separate HDL file (separate HDL module)

32. Hierarchical/Modular Design Decoder.v Top Most Design Unit KeyIN.v Sub-Blocks (cells) A B SevenSegmenDec.v Each unit is coded in a separate HDL file (separate HDL module)

33. Modular Design

34. HDL Code

35. Module Instances - Format Instantiation template: <original_module_name> <name_of_instance> (<instance_internal_port_list>); In another module named DFF2, we want to use the DFF module. So, we should write: Example • module DFF (data, clock, q); • input data, clock; • output q; • … • <the function of D flip-flop> • … • endmodule • module DFF2 (d, clk, q); • input [1:0] d; • output [1:0] q; • … • DFF dff1 (d[0], clk, q[0]); • DFF dff2 (d[1], clk, q[1]); • … • endmodule instances

36. Module Instances - Purpose • Nested module instances support top-down design hierarchy Example: Verilog code (top-down approach) of full_adder • module full_adder (sum, c_out, a, b, c_in) • input a, b, c_in; • output sum, c_out; • half_adder HA1 (w1, w2, a, b); • half_adder HA2 (sum, w3, c_in, w1); • or (c_out, w2, w3); • endmodule top-down approach nested module instances

37. Top-down Design & Nested Modules Exercise: Based on full_adder code in previous slide, label the following design blocks: Given: full_adder half_adder a sum c_out b module half_adder (sum, c_out, a, b) HA2 half_adder HA1 half_adder +

38. Verilog Primitives • Verilog has a set of 26 predefined functional models of common combinational logic gates called primitives • Most basic functional objects • Names are reserved words in Verilog

39. Verilog Language Rules Identifiers • Identifiers (name) in Verilog is composed of space-free sequence of upper- and lowercase letters from the alphabet, the digits (0-9), the underscore and the $ symbol • Verilog is case sensitive language • Example: • and2 • counter3_updn

40. Verilog Language Rules White Space • Used to format text of a model • However, might not separate contiguous characters of identifier or keyword, or digits of number

41. Verilog Language Rules Statement Termination • Text of Verilog model is placed between module and endmodule • Statements in Verilog is terminated by a semicolon (;) • These statements includes: • data types of signals • other elements that describe structural details of a model • executable procedural statements used by simulator to determine the value of signal

42. Verilog Language Rules Comments • Many designers always neglect to put comments in the code • Comments is an important form of documentation on the functionality/objective of the code • It helps in making the code readable • Single line comments begins with the symbol // • Multiple line comments begins with /* and ends with */

43. Verilog Language Rules (Verilog version 2001) Example: • module ANDgate ( • input A, B, • output reg Y); • always @ (A or B) • begin • Y = A & B; // A and B • end • endmodule • module ANDgate ( • Input A, B, • output reg Y); • always @ (A or B) • begin • Y = (A & B)|( A | B); /* (A and B) • or • (A or B) */ • end • endmodule

44. Verilog Language Rules Numbers • Numbers in Verilog can be represented as: • Real numbers • Integer numbers • Base numbers (binary, octal, hex, decimal) • Two types of numbers: • Sized numbers • Unsized numbers How to write in module: module ……; …. integer A, B, C; A = 4’b0101; B = 5’o14; C = 8’ha5; D = 5’d14; …. endmodule

45. Verilog Language Rules • Sized numbers <size> ‘<base_format> <number> Decimal value – specifies # bits in the number Decimal (‘d or ‘D) Hex (‘h or ‘H) Binary (‘d or ‘D) Octal (‘d or ‘D) Consecutive digits (0, 1, 2, 3, 4 5, 6, 7, 8, 9, a, b, c, d, e, f) Example: 4’b1111 // 4-bit binary number 12’habc // 12-bit hex number 16’d255 // 16-bit decimal number DIY: 8’d123 // number?

46. Verilog Language Rules • Unsized numbers Size? Have default value of bits (depends to simulator or machine ≥ 32 bit) ‘<base_format> <number> Decimal (‘d or ‘D) Hex (‘h or ‘H) Binary (‘d or ‘D) Octal (‘d or ‘D) Consecutive digits (0, 1, 2, 3, 4 5, 6, 7, 8, 9, a, b, c, d, e, f) Example: ‘hc3 // 32-bit hex number ‘oc3 // 32-bit octal number 765 // 32-bit decimal number DIY: ’d123 // number?

47. Verilog Language Rules • X or Z values • X : unknown value • Z : high-impedance value • Very important in modeling real circuit • Use the same sized & unsized number format Example: 12‘h13x // 12-bit hex number, with 4 LSBs unknown 6‘hx // 6-bit unknown hex number 32’bz // 32-bit high-impedance number 6‘hx3 // What is the equivalent number?

48. Verilog Data Types

49. Verilog Data Types

50. ‘wire’ Usage • When using ‘assign’ statement, always use wire declaration Example: • module ANDgate (A, B, Y); • input A, B; • output Y; • wire Y; // optional • assign Y = A & B; • endmodule IMPORTANT NOTE! Any identifier without type declaration has default-type wire Y is constantly updated with value from A and B