Embedding of Asynchronous Wave Pipelines into Synchronous Data Processing

1. Embedding of Asynchronous Wave Pipelines into Synchronous Data Processing Stephan Hermanns, Sorin Alexander Huss University of Technology Darmstadt, Germany

2. Some Notations...

3. Asynchronous Wave Pipeline (AWP) Wave Latch Wave Latch Wave Logic Data req_in req_out matched delay • More than one data and request propagating coherently • One-sided cycle time constraint • Delay must track logic over PTV corners

4. Circuits • Logic style used has to minimize delay variation • Earlier work focused on bipolar logic (ECL, CML), but CMOS is mainstream • Static CMOS is not well suited for wave piping, fixing the problem results in more power and slower speed • Pass transistor logic gives slopy edges thereby introducing delay variation • Dynamic logic is attractive as only output high transition is data-dependant, output pulldown is done by precharge • What is needed is a dynamic logic family without precharge overhead: SRCMOS

5. SRCMOS • Distinguishing property of our SRCMOS circuits: precharge feedback is fully local, and NMOS trees are delay balanced output N inputs

6. Generic Synchronous Pipeline Latch/Reg Latch/Reg Logic Data Clk

7. Static  Pulse Conversion: Transistor Level Data input has to be stable during evaluation time teval after rising edge ofclka or clkb Pulse width is defined by feedback path of SRCMOS Generates pulse according to data input after rising edge of clka or clkb

8. Pulse  Static Conversion: Schematic Level Data pulse is catched asynchronous and output statically in synchronization with request pulse

9. Pulse  Static Conversion: Transistor Level

10. Request Generation: Register is omitted Input to Register is stable in [MTclk-tsetup,MTclk+thold] This has to be sufficient to Pulse Generator to evaluate Input Data Hold time thold is crucial  Further Investigation

11. Request Generation: Register is kept Only non-inverting outputs used to form clock-like Signal to Pulse-Gen.  no Skew Request and Data Pulses are generated uniformly No additionally Reset of Register needed Delay Variations among FFs are handled simply Input to Pulse-Gen. is to be stable after rising clock edge

12. Static  Pulse Conversion: Delay

13. Pulse  Static Conversion: Delay

14. Overall Delay Includes delay of D-FF static  pulse converter empty AWP logic pulse  static converter Problem: Delay variation may as large as clock period Tclk

15. Request Pulses: Maximum Skew Request skew primarly results of skew between rising edges at clka and clkb input of pulse generator Exponential behavior at low level

16. Conclusion • Integration of pulsed logic into environment of statical data • Generation of data pulses by different ways • Generation of request pulses coherently to data pulses with low skew • Conversion of pulsed data back to statical data • Further investigation is needed: • synchronization of static output and output register‘s clock • Possibility to replace register by pulse generator generally