Competitive Power

1. Competitive Power • Power Overview • Understanding Evaluation Methodology • Benefits of Low Power • Performance • Density • Package Options • Reliability • Conclusion

2. Performance And Density Die Temp 150 oC 125 oC 100 oC Power Consumption Overview • Higher speed/density requires more power, leading to higher junction temp. • Junction temperature is limited to 125oC for plastic & 150oC for ceramic packages • Power directly limits: • System performance • Design density • Package options • Device reliability

3. Power History • As devices get larger & faster, power goes UP • 1st generation FPGAs had: • Lower performance • Lower power requirements • No package power concerns • High density FPGAs have: • Much higher performance • Higher power requirements • Package power limit concerns exist Package Power Limit PMAX High Density Low Density Real World Design Power Consumption Performance (MHz)

4. Estimating Power Is Complex • Power consumption is completely design dependent and is affected by: • System performance (switching frequency) • Design density (number of interconnects) • Design activity (% of interconnects switching) • Logic block and interconnect structure • Supply voltage • No single benchmark can emulate all design conditions realistically; they must be used as guideline only

5. Device Power Comparison • To compare device power between different architectures, the counter methodology is used • Fill the device with 16-bit counters with no loads • Measure active ICC versus frequency • Solve the equation for “K” • Both Xilinx devices and Altera’s 10K50s were measured to verify methodology • The resulting Xilinx K factors are directly comparable with the Altera “K” factors, ratio of “K” factors = ratio of current!

6. Altera’s Methodology forEstimating Active Power Active ICC = K x fMAX x N x %TOG • ICC = Active ICC in uA. • K = Scale Factor in uA/(MHz*LE) • fMAX = Maximum operating frequency In MHz • N = Number of Logic Cells (LEs or 1/2CLBs) used in design • %TOG = Percent of Logic Cells toggling “K” Factor Is Direct Indicator Of Device Architecture Power Efficiency. Equation Gives Rough Estimate Of Active ICC Only.

7. “K” Factor Comparison • Low “K” is low current • “K” factor is directly related to the device current based on architecture, process and user’s circuit design • At high densities a low “K” factor is mandatory! • Ratio of “K” factors = ratio of current! Altera 10K “K” Factor (Current) Nearly Twice Xilinx 4KEX *Source: Altera K Factors From Flex8K and Flex10K Data Sheets

8. Xilinx vs. Altera FLEXInterconnect Technology Xilinx FPGA Architecture Altera FLEX Architecture Logic Block 1 Logic Block 2 Logic Block 3 Logic Block 4 Logic Block 1 Logic Block 2 Logic Block 3 Logic Block 4 A A B C B C “Segmented” Interconnect Lines “Non-Segmented” Interconnect Lines • Variable length Interconnect lines • 1 Segmented line required to connect 4 logic cells • Lower capacitance on short lines means lower power • Fixed Length Interconnect Lines • 3 Single Signal lines required to connect 4 logic cells • Higher capacitance on each net means higher power

9. Package Power Limit 16-Bit Counter 8-Bit Counter PMAX Real World Design Power Consumption Performance (MHz) Understanding 8/16-BitCounter Benchmarks • Benchmark fills device with 8 or 16-bit counters • Predictable # lines toggling • 12.5% for 16-bit counter • 25% for 8-bit counter • Many real designs 12%-25% • Package power limit determined by max junction temp. & package thermal resistance (0JA)

10. Xilinx 4KXL >3X Faster than Altera 10K Typical Power Consumption by Frequency 2000 Package Limit 10K100 XC4062XL Current (mA) 1000 0 0 20 MHz 40 MHz 60 MHz 80 MHz 100 MHz Performance Package = 503/475 PGA

11. Xilinx 4KEX 2X Faster than Altera 10K Typical Power Consumption by Frequency 1000 Package Limit 10K50 XC4036EX 500 Current (mA) 0 20 MHz 40 MHz 60 MHz 0 Performance Package = 240 HQFP

12. Xilinx 4KXL 1.5X Faster than Altera 10KV Typical Power Consumption By Frequency 1000 XC4036XL Package Limit 10K50V Current (mA) 500 0 25 MHz 50 MHz 75 MHz 100 MHz 0 Performance Package = 208 HQFP

13. Xilinx 4KE 1.5X Faster than Altera 10K Typical Power Consumption by Frequency 1000 Package Limit XC4025E 10K40 500 Current (mA) 0 20 MHz 40 MHz 60 MHz 0 Performance Package = 240 HQFP Full 8 bit and 16 bit counter benchmarks used for range

14. Design Density Comparison • Another way of looking at the solution is to evaluate how much logic can be placed in a device while achieving a specific performance goal • The density vs. frequency plots provide a quick way to estimate the capacity of a device/package combination

15. Xilinx 4KEX 2X Logic Capacity Of Altera 10K Maximum Density At 50MHz 1000 Package Limit 10K50 XC4036EX 500 Current (mA) 0 2000 1000 3000 0 Density (LCs) Max LCs For Device; 10K50 = 2880, XC4036EX = 3078 Package = 240 HQFP

16. Xilinx Lower Power Offers More Package Options • FLEX 10K100 is only available in PGA 503! • Power dissipation unacceptable for other packages • Altera forced to specify package with fan & heat sink attached • Who uses PGAs in production? • Expensive • Large • XC4062XL is available in many package configurations! • HQ240, BG432, BG560, PG475

17. Xilinx Lower Power = Higher Reliability FIT Rates • FIT: failures in 109 device hrs • Lower the FIT rate the better • As junction temperature increases, FIT rate increases dramatically • Device reliability decreases rapidly as junction temp. increases above 100oC FIT rate acceleration based on activation energy of 0.9 eV, Base FIT rates from Xilinx and Altera Quality Reports

18. Xilinx Lower Power Offers 360X Better Reliability • A design which does not stress any of the device limits: • Altera 10K50 in 240 RQFP and Xilinx 4036EX in 240 HQFP run under the following conditions: • 120 16-bit counters in device at 30 MHz system speed • 5.0 Volts supply, 50oC ambient temperature • Altera device runs at 125oC junction, Xilinx at 70oC • All values within device maximum limits! • Reliability evaluation • Xilinx solution gives 360x better reliability (3600/10) • Xilinx 4036XL will give 1200x better reliability

19. Conclusion • Xilinx consistently provides superior performance limits while using low cost plastic packages • Xilinx XC4000E & EX families offer best power/speed/density tradeoffs in the industry • Xilinx XC4000XL delivers the industry-leading performance at very high densities • Using Altera’s own methodology, Xilinx XC4000EX devices dissipate 1/2 power of Altera Flex 10K parts • 4KXL devices draw <1/3 power of Flex 10K parts

20. Appendix

21. 16 Bit Counter Example Q Q Q Q Q Q Q0 Q1 Q2 Q13 Q14 Q15 How do you get 12% toggle rate for a 16-Bit Counter? Q0 toggles each clock period, it contributes 1/16 = .0625 Q1 toggles every 2nd clock period, it contributes 0.5/16 = .03125 Q2 toggles every 4th clock period, it contributes 0.25/16 = .015625 Q3 toggles every 8th clock period, it contributes 0.125/16 = .007813 Q4 ... Q15 ... Sum All Contributions: .12 Total Note: For 8 Bit Counter, Each Contribution Is x/8

22. Determining Max Package Current • Find From Data Sheet On Package The 0JA • Determine The Max Ambient Temperature (TA in oC) • Determine The Max Junction Temperature (TJ in oC) • Calculate The Max Package Current; • IMaxPkg = [(TJ - TA) / 0JA ] / VCC

23. Understanding the Comparison Graphs The maximum current the package can handle without exceeding maximum junction temperature Typical Power Consumption by Frequency Package Limit 16-bit limit The range of currents expected in most real designs, upper limit defined by 8-bit counters and lower limit by 16-bit counters Current (mA) 8-bit limit Performance Notes about graph conditions Package = 240 HQFP