Design and Performance of the 6 GS/s Waveform Digitizing Chip DRS4

1. Design and Performance of the 6 GS/s Waveform Digitizing Chip DRS4 at 40 mW per channel Stefan Ritt Paul Scherrer Institute, Switzerland

2. Switched Capacitor Array • Cons • No continuous acquisition • No precise timing • External (commercial) ADC needed • Pros • High speed (6 GHz) high resolution (11.5 bit resol.) • High channel density (9 channels on 5x5 mm2) • Low power (10-40 mW / channel) • Low cost (~ 10$ / channel) Dt Dt Dt Dt Dt IEEE/NSS Dresden

3. DRS4 • Fabricated in 0.25 mm 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard • 8+1 ch. each 1024 cells • Differential inputs,differential outputs • Sampling speed 500 MHz … 6 GHz,PLL stabilized • Readout speed 30 MHz, multiplexedor in parallel IEEE/NSS Dresden

4. ROI readout mode delayed trigger stop normal trigger stop after latency stop Trigger Delay 33 MHz e.g. 100 samples @ 33 MHz  3 us dead time(2.5 ns / sample @ 12 channels) readout shift register Patent pending! IEEE/NSS Dresden

5. Daisy-chaining of channels Domino Wave Generation Channel 0 – 1024 cells Channel 1 – 1024 cells Channel 2 – 1024 cells Channel 3 – 1024 cells Channel 4 – 1024 cells Channel 5 – 1024 cells Channel 6 – 1024 cells Channel 7 – 1024 cells Deeper Sampling Depth can be reached by multiplexing channels IEEE/NSS Dresden

6. Daisy-chaining of channels Domino Wave Domino Wave clock clock enable input enable input 1 Channel 0 0 Channel 0 enable input enable input 0 Channel 1 1 Channel 1 Channel 2 0 Channel 2 1 Channel 3 Channel 3 1 0 Channel 4 Channel 4 0 1 Channel 5 Channel 5 1 0 Channel 6 Channel 6 0 1 Channel 7 Channel 7 1 0 IEEE/NSS Dresden

7. 1 Channel 0 1 Channel 1 1 Channel 2 1 Channel 3 1 Channel 4 1 Channel 5 1 Channel 6 1 Channel 7 Single Channel Domino Wave clock DRS4 0 Channel 0 0 Channel 1 Channel 2 0 Connect channels externally to keep high bandwidth limited by bond wires (PCB or analog switches) Channel 3 0 Channel 4 0 Channel 5 0 Channel 6 0 Channel 7 0 DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells IEEE/NSS Dresden

8. DRS4 DRS4 DRS4 SRIN SRIN SRIN SROUT SROUT SROUT Chip Daisy Chaining Virtually unlimitedsampling depth IEEE/NSS Dresden

9. readout Channel 0 1 Channel 0 1 0 1 Channel 1 Channel 1 Channel 2 Simultaneous Write/Read FPGA 0 Channel 0 0 Channel 1 8-foldanalog multi-eventbuffer Channel 2 0 Channel 3 0 Channel 4 0 Channel 5 0 Channel 6 0 Channel 7 0 Expected crosstalk ~few mV IEEE/NSS Dresden

10. DRS4 MUX Trigger an DAQ on same board • Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS • FPGA can make local trigger(or global one) and stop DRSupon a trigger • DRS readout (6 GHz samples)though same 8-channel FADCs global trigger bus trigger FPGA DRS FADC12 bit 65 MHz analog front end LVDS SRAM “Free” local trigger capability without additional hardware IEEE/NSS Dresden

11. DRS4 Test Results

12. On-chip PLL Simulation loop filter DRS4 Vspeed Phase detector up down Measurement Reference Clockfclk = fsamp / 2048 • PLL jitter « 100 ps (Spartan-3 jitter 150 ps) • “Dead Band” free • Does not lock on higher harmonics IEEE/NSS Dresden

13. Bandwidth • Bandwidth is determined by bond wire and internalbus resistance/capacitance: • 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) QFP package finalbus width 850 MHz (-3dB) Simulation Measurement IEEE/NSS Dresden

14. Timing jitter • Inverter chain has transistor variations  Dti between samples differ “Fixed pattern aperture jitter” • “Differential temporal nonlinearity” TDi= Dti – Dtnominal • “Integral temporal nonlinearity”TIi = SDti – iDtnominal • “Random aperture jitter” = variation of Dti between measurements Dt1 Dt2 Dt3 Dt4 Dt5 TD1 TI5 IEEE/NSS Dresden

15. Fixed jitter calibration • Fixed jitter is constant over time, can be measured and corrected for • Several methods are commonly used • Most use sine wave with random phase and correct for TDi on a statistical basis IEEE/NSS Dresden

16. Fixed Pattern Jitter Results • TDi typically ~50 ps RMS @ 5 GHz • TIi goes up to ~600 ps • Inter-channel variation on same chip is very small since all channels are driven by the same domino wave IEEE/NSS Dresden

17. Random Jitter Results • Sine curve frequency fitted for each measurement (PLL jitter compensation) • Encouraging result for DRS3:2.7 ps RMS (best channel)3.9 ps RMS (worst channel) • Differential measurement t1 – t2 adds a 2, needs to be verified by measurement • Measurement of n points on a rising edge of a signal improves by n Measurements for DRS4 currently going on, expected to be slightly better IEEE/NSS Dresden

18. Experiments using DRS chip MEG 3000 channels DRS2 MAGIC-II 1200 channels DRS2 BPM for XFEL@PSI 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned) IEEE/NSS Dresden

19. 64-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 6 GHz Availability • DRS4 will become available in larger quantities in November 2008 • Chip can be obtained from PSI on a “non-profit” basis • Delivery “as-is” • Reference design (schematics) from PSI • Costs ~ 10-15$/channel • VME boards from industry in 2009 ext. Trigger Input DRS4 USB 2.0 IEEE/NSS Dresden

20. Conclusions • Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future • DRS4 chip solves all known issues of DRS3 and adds more flexibility • DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 3 ps timing resolution • ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this technology http://midas.psi.ch/drs IEEE/NSS Dresden

22. A bit of history… MEG Experiment searching for me g down to 10-13 DRS1 2001 DRS2 2004 DRS3 2006 DRS4 2008 3000 Channels with GHz sampling IEEE/NSS Dresden

23. DRS4 packaging DRS4 flip-chip DRS4 DRS3 4.2 mm 9 mm 18 mm IEEE/NSS Dresden

24. Solution: Clear before write write clear “Residual charge” problem R After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses Implemented in DRS4 “Ghost pulse” 2% @ 2 GHz IEEE/NSS Dresden

25. Sine Curve Fit Method i yji : i-th sample of measurement j aj fj ajoj : sine wave parameters bi : phase error  fixed jitter • “Iterative global fit”: • Determine rough sine wave parameters for each measurement by fit • Determine bi using all measurements where sample “i” is near zero crossing • Make several iterations j S. Lehner, B. Keil, PSI IEEE/NSS Dresden

26. Signal-to-noise ratio (DRS3!) • “Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA • SNR: • 1 V linear range / 0.35 mV = 69 dB (11.5 bits) Offset Correction IEEE/NSS Dresden

27. Global Timing Clock domino wave signal 20 MHz Reference clock 8 inputs PMT hit shift register Domino stops after trigger latency Reference clock MUX PLL jitter O(100ps)  Timing difference between signals sampled by different chips need a global reference clock IEEE/NSS Dresden

28. Datasheet http://midas.psi.ch/drs IEEE/NSS Dresden

29. G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) Interleaved sampling 6 GSPS * 8 = 48 GSPS delays (200ps/8 = 25ps) Possible with DRS4 if delay is implemented on PCB IEEE/NSS Dresden

30. Comparison with other chips IEEE/NSS Dresden

31. On-line waveform display S848 PMTs “virtual oscilloscope” template fit click pedestal histo IEEE/NSS Dresden

32. Constant Fraction Discr. Delayed signal Inverted signal Sum Clock 12 bit Latch Latch Latch Latch + Latch Latch S + <0 & MULT 0 IEEE/NSS Dresden