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Microprocessor Clocking

Microprocessor Clocking. DEC Alpha Clock Distribution. Case Study: Pentium 4. Core only; I/O not included. Pentium 4 Description. Two PLLs I/O Core Clock Distribution Network Skew optimized Jitter reduced  2 GHz core;  4 GHz rapid execution engine Pulsed and non-pulsed clocks

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Microprocessor Clocking

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  1. Microprocessor Clocking

  2. DEC Alpha Clock Distribution

  3. Case Study: Pentium 4 Core only; I/O not included

  4. Pentium 4 Description • Two PLLs • I/O • Core • Clock Distribution Network • Skew optimized • Jitter reduced •  2 GHz core;  4 GHz rapid execution engine • Pulsed and non-pulsed clocks • I/O PLL has glitch detection and protection

  5. Pentium 4 Description • 0.18 µm • Six metal layers • CMOS • 42 million transistors

  6. Architecture Core Clocks Fast: 4 GHz LCDs Med: 2 GHz LCDs system clocks Clock Dist Core PLL LCDs Slow: 1 GHz LCDs: Local Clock Drivers LCDs 1x: 100 MHz LCDs 2x: 200 MHz I/O PLL Clock Dist 4x: 400 MHz LCDs I/O Clocks

  7. 3 Clock Spines Large die required 3 spines.

  8. From PLL Binary Clock Distribution Each leaf node is an independent clock domain

  9. Systemic Skew • Within-die Variations • Channel Length • Threshold • Width • Interlayer Dielectric Thickness • Non-ideal Placement • Modeling and Extraction Errors

  10. Skew Optimization • 47 Adjustable Delay Domain Buffers • Accessible from a test access port • Phase Detector Network • 46 Phase Detectors

  11. Adjustable Delay Domain Buffers

  12. Adjustable Delay Domain Buffers SEU

  13. Skew Optimization Circuit Adjustable Delay Domain Buffer To Test Access Port DB1 Phase Detector DB2 Phase Detector To Local Clock Drivers DB3 Binary Distribution Trees Phase Detector DB4 Phase Detector DB5 To Test Access Port

  14. Skew Trimming • Domain Buffer at the center of the die is the primary reference • Other levels: secondary, tertiary, final • Secondary aligned to primary • Then tertiary aligned to secondary • Then final buffers aligned to tertiary level

  15. Skew Trimming (cont’d) • Initial skew about 64 ps for a particular die • Accumulated skew, after adjustment, about ± 8 ps • Scheme can force deliberate skew • Improves performance, optimium pipelining

  16. Skew Trimming (cont’d) Primary Reference Domain Clock Buffer Phase Detectors Secondary References Tertiary Reference Final Stage Accumulated error < ± 8 ps

  17. Medium Speed Pulse Generator Pulse width adjustable 3. Turned on, driving clock back low 4. Self-resets Gating, power management 2. Tri-states pull-down path High speed version works off both edges of the clock, doubling the frequency. 1. Pulled down, driving clock high

  18. Pentium 4 Closing • Presented basics of core clock distribution system • Did not present: • Logic Design • I/O sections • Exercise: Analyze SEU implications of the structures just discussed

  19. Other examples available, add when we get time Itanium AMD

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