Clocking & Timing

1. Clocking & Timing EE116B (Winter 2000): Lecture # 18 March 9, 1999

2. The Clock Skew Problem

3. Delay of Clock Wire

4. Constraints on Skew

5. Clock Constraints in Edge Triggered Logic

6. Positive and Negative Skew

7. Clock Skew in Master-Slave2-Phase Design

8. Clock Skew in 2-Phase Design

9. How to Counter Clock Skew?

10. Clock Distribution

11. Clock Network with Distributed Buffering

12. Example: DEC Alpha 21164 • Clock frequency: 300MHz • 9.3 Million transistors • Total clock load: 3.75 nF • Power in clock distribution network: 20W • out of 50W • Uses two level clock distribution • single 6-stage buffer at the center of the chip • secondary buffers drive left and right side clock grid in Metal3 and Metal4 • Total driver size: 58 cm !

14. Clock Skew in Alpha Processor

15. Self-timed and Asynchronous Design • Functions of clock in synchronous design • acts as completion signal • ensures the correct ordering of events • Truly asynchronous design • completion is ensured by careful timing analysis • ordering of events is implicit in logic • Self-timed design • completion ensured by a completion signal • ordering imposed by handshaking protocol

16. Self-timed Pipelined Datapath

17. Completion Signal Generation

18. Completion Signal Generation Using Redundant Signal Encoding

19. Completion Signal UsingDCVSL Logic

20. Self-timed Adder

21. Hand-shaking Protocol

22. Event Logic: the Muller C-Element

23. 2-phase Handshake Protocol

24. Example: Self-timed FIFO

25. 4-phase Handshake Protocol(or, RTZ)

26. 4-phase Handshake Protocol (Implementation)

27. Asynchronous-Synchronous Interface

28. A Simple Synchronizer

29. Synchronizer: Output Trajectories

30. Simulated Trajectory vs. One Pole Model

31. Mean Time to Failure

32. Example

33. Cascaded Synchronizers Reduce MTF

34. Arbiters

35. Synchronization at System Level

36. Skew of Local Clocks vs. Reference

37. Phase-Locked Loop Based Clock Generator

38. Ring Oscillator

39. Example of PLL-generated Clock