Digital PM Demodulator for Brazilian Data Collecting System

1. Digital PM Demodulator for Brazilian Data Collecting System José Marcelo L. Duarte – UFRN – Natal, Brazil Francisco Mota das Chagas – UFRN – Natal, Brazil Manoel J. M. de Carvalho – INPE – Natal, Brazil

2. Contents • Introduction • BDCS Signal Characteristics • Signal Processing System • Split Loop Architecture • Loop Filter Project • Phase Detector Low Pass Filters Project • Implementation • Simulations • Conclusions and Final Considerations

3. Introduction • This work describes the design and implementation of a digital PM demodulator for processing LEO satellite signals from Brazilian Data Collecting System (BDCS). • Altera Cyclone II DSP Development Kit, equipped with EP2C70 FPGA, was used for implementation. • Demodulation is done by second order Digital PLL (Phase-Locked Loop) with Split-Loop architecture and –π to +π linear phase detector made by a cartesian to polar converter.

4. BDCS Signal Characteristics

6. Signal Processing System

7. DPLL Standard Architecture

8. Split Loop Architecture • In standard PLL architecture, delay is present in both proportional and integral action possibly causing instabilities. • Split-Loop (Gustrau and Hoffmann, 99) is a second order PLL architecture where the PI loop filter is divided into proportional and integral parts, making two loops.

9. Split-Loop Architecture

10. Split-Loop Architecture • Since the integral output varies slowly, phase delay due to low pass filtering on this signal is negligible. Thus, Split-Loop architecture is less affected by phase detector low pass filtering delay than the standard architecture. This has allowed use of a narrower filter in phase detector, without compromising system stability.

11. Split-Loop Linear Model

12. Split-Loop Linear Model

13. Loop Filter Project • Choice of KP and KI parameters was made designing an analog second order PLL and mapping their poles to the discrete time domain. • Performance specifications chosen: • Damping Factor (ξ) = 1.2; • Lock Range = 30 kHz • PLL Band (ω3db) results 11,17 kHz. Thus, PLL will not have dynamic to follow the modulation, so demodulated signal will appear in error signal. • Steady state phase error due to Doppler Effect results Θe = 7.6·10-6 rad

14. Phase Detector Low Pass Filters Project • FIR filters with linear phase response were used to avoid phase deformation; • Decimation by 16 was done to reduce the number of necessary taps to implement the filters. • FIR 1 serves as anti-aliasing filter; • FIR 2 has ±0.5 dB gain region from 0 to 125 kHz and -60 dB gain cut region starting at 240 kHz.

15. Implementation • Software NCO Compiler and FIR Filter Compiler from Altera were used to generate HDL code for NCO and FIR filters respectively; • The cartesian to polar converter was implemented using CORDIC algorithm operating on vectoring mode; • Quartus II software was used to program the FPGA;

16. Simulation • BDCS signal model • DSP Builder • Hardware in the Loop (HIL) • Correlation • Delay of 25 us

17. Simulation with SNR = -7.5 dB

18. Simulation with SNR = -13.5 dB

19. Conclusions and Final Considerations • Split loop architecture has improved output SNR and system performance. • Simulations demonstrated that the demodulator works as expected, but improvement need to be done, since the linear operation limit of the DPLL is being exceeded when input SNR is lower than -10 dB.