14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 13 Basics of Cache

1. 14:332:331Computer Architecture and Assembly LanguageSpring 2005Week 13Basics of Cache [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

2. Head’s Up • This week’s material • Basics of caches • Reading assignment – PH 7.2 • Reminders

3. Review: A Typical Memory Hierarchy • By taking advantage of the Principle of Locality: • Present the user with as much memory as is available in the cheapest technology at the access speed offered by the fastest technology. On-Chip Components Control eDRAM Secondary Memory (Disk) Instr Cache Second Level Cache (SRAM) ITLB Main Memory (DRAM) Datapath Data Cache RegFile DTLB Speed: 1 ns 2 ns 10 ns 50 ns 1,000 ns Size: 128 B 64KB 256KB 4 GB TB’s Cost: highest lowest

4. Lower Level Memory Upper Level Memory To Processor Blk X From Processor Blk Y Review: Principle of Locality • Temporal Locality • Keep most recently accessed data items closer to the processor • Spatial Locality • Move blocks consisting of contiguous words to the upper levels • Hit Time << Miss Penalty • Hit: data appears in some block in the upper level (Blk X) • Hit Rate: the fraction of accesses found in the upper level • Hit Time: Time to access the upper level = RAM access time + Time to determine hit/miss • Miss: data needs to be retrieve from a lower level block (Blk Y) • Miss Rate = 1 - (Hit Rate) • Miss Penalty: Time to replace a block in the upper level with a block from the lower level + Time to deliver this block to the processor • In general, Average Access Time: • = Hit Time + Miss Penalty x Miss Rate

5. Review: How is the Hierarchy Managed? • registers <-> memory • by compiler (programmer?) • cache <-> main memory • by the hardware • main memory <-> disks • by the hardware and operating system (virtual memory) • by the programmer (files)

6. Cache • Two questions to answer (in hardware): • Q1: How do we know if a data item is in the cache? • Q2: If it is, how do we find it? • First method: • Direct mapped • For each item of data at the lower level, there is exactly one location in the cache where it might be (i.e., lots of items at the lower level share locations in the upper level) • Block size is one word of data • Mapping: (word address) modulo (# of words in the cache)

7. Caching: A Simple First Example 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Main Memory Cache Valid Tag Data 00 01 10 11 Q2: How do we find it? Use low order 2 memory address bits to determine which cache block (i.e., modulo the number of blocks in the cache) Q1: Is it there? Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache

8. 01 4 11 14 Direct Mapped Cache • Consider the main memory reference string 0 1 2 3 4 3 4 14 Start with an empty cache - all blocks marked as not valid 0 miss 1 miss 2 miss 3 miss 00 Mem(0) 00 Mem(1) 00 Mem(0) 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) miss 3 hit 4 hit 14 miss 4 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3)

9. 01 4 00 01 0 4 00 0 01 4 00 0 01 4 Another Reference String Mapping • Now consider the main memory reference string 0 4 0 4 0 4 0 4 • Ping pong effect due to conflict misses - two memory locations that map into the same cache block Start with an empty cache - all blocks marked as not valid miss miss miss miss 0 4 0 4 00 Mem(0) 00 Mem(0) 01 Mem(4) 00 Mem(0) 4 0 4 0 miss miss miss miss 01 Mem(4) 00 Mem(0) 01 Mem(4) 00 Mem(0)

10. Sources of Cache Misses • Compulsory (cold start or process migration, first reference): first access to a block • “Cold” fact of life, not a whole lot you can do about it • If you are going to run “billions” of instruction, Compulsory Misses are insignificant • Conflict (collision): • Multiple memory locations mapped to the same cache location • Solution 1: increase cache size • Solution 2: increase associativity • Capacity: • Cache cannot contain all blocks accessed by the program • Solution: increase cache size

11. Byte offset 31 30 . . . 13 12 11 . . . 2 1 0 Tag 20 Data 10 Hit Index Index Valid Tag Data 0 1 2 . . . 1021 1022 1023 20 32 MIPS Direct Mapped Cache Example • One word/block, cache size = 1K words

12. Handling Cache Misses • Handling hit is trivial • Handling misses needs to stall the processor • Upon an instruction cache miss • Send the original PC value (current PC – 4) to the memory • Instruct main memory to perform a read and wait for the memory to complete its access • Write the cache entry, putting the data from memory in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on • Restart the instruction execution at the first step, which will re-fetch the instruction, this time finding it in the cache • Similar for data cache miss

13. Handling Writes • The cache and memory are inconsistent when their values (of the same data) are different • A simple solution: write through • Write to both the cache and the memory at the same time • Poor performance. Every store instruction needs to stall the processor (a memory access can take 100 CPU cycles) • Alternative: write back • Write to the cache; write to the memory when the cache block is replaced later.

14. Cache Summary • The Principle of Locality: • Program likely to access a relatively small portion of the address space at any instant of time • Temporal Locality: Locality in Time • Spatial Locality: Locality in Space • Three Major Categories of Cache Misses: • Compulsory Misses: sad facts of life. Example: cold start misses • Conflict Misses: increase cache size and/or associativity Nightmare Scenario: ping pong effect! • Capacity Misses: increase cache size • Cache Design Space • total size, block size, associativity (replacement policy) • write-hit policy (write-through, write-back) • write-miss policy (write allocate, write buffers)

15. Memory Systems that Support Caches • The off-chip interconnect and memory architecture can affect overall system performance in dramatic ways. One word wide organization (one word wide bus and one word wide memory) on-chip CPU • Assume • 1 clock cycle (2 ns) to send the address • 25 clock cycles (50 ns) for DRAM cycle time, 8 clock cycles (16 ns) access time • 1 clock cycle (2ns) to return a word of data • Memory-Bus to Cache bandwidth • number of bytes accessed from memory and transferred to cache/CPU per clock cycle Cache bus 32-bit data & 32-bit addr per cycle Memory

16. One Word Wide Memory Organization • If the block size is one word, then for a memory access due to a cache miss, the pipeline will have to stall the number of cycles required to return one data word from memory cycle to send address cycles to read DRAM cycle to return data total clock cycles miss penalty • Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock on-chip CPU 1 25 1 27 Cache bus Memory 4/27 = 0.148

17. 25 cycles 25 cycles 25 cycles 25 cycles One Word Wide Memory Organization, con’t • What if the block size is four words? cycle to send 1st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty • Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock on-chip 1 4 x 25 = 100 1 102 CPU Cache bus Memory (4 x 4)/102 = 0.157

18. 25 cycles 25 cycles 25 cycles 25 cycles Interleaved Memory Organization • For a block size of four words cycle to send 1st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty on-chip 1 25 + 3 = 28 1 30 CPU Cache bus Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 • Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock (4 x 4)/30 = 0.533

19. DRAM Memory System Summary • Its important to match the cache characteristics • caches access one block at a time (usually more than one word) • with the DRAM characteristics • use DRAMs that support fast multiple word accesses, preferably ones that match the block size of the cache • with the memory-bus characteristics • make sure the memory-bus can support the DRAM access rates and patterns • with the goal of increasing the Memory-Bus to Cache bandwidth