Lecture 16

1. Lecture 16 • Timing • Terminology • Timing issues • Asynchronous inputs

2. Terminology • Setup time tsu: Amount of time the input must be stable before the clock transitions high (or low for negative-edge triggered FF) • Hold time th: Amount of time the input must be stable after the clock transitions high (or low for negative-edge triggered FF)

3. Terminology • Clock width tw : Minimum clock width that must be met in order for FF to work properly • Propagation delays tp-lh and tp-hl: Delay between clocking event and change in output (high to low, low to high) • Longer than hold time

4. tsu th th tsu D tw CLK Q tp-hl Terminology

5. In Q0 Q1 Clk tsu tsu tp-lh tp-hl th th Cascading flip-flops IN Q1 Q0 D Q D Q > > CLK Order can’t be reversed else Q1 will not have its required hold time tp-hl , tp-lh > th tp +tsu <tcycle

6. Cascading flip-flops • Flip-flop propagation delays exceed hold times • Second stage commits its input before Q0 changes

7. System considerations • Basic rules for correct timing • Clock flip-flops synchronously (all at the same time) • No flip-flop changes state more than once per clock cycle • FF propagation delay > hold time • Avoid mixing positive-edge triggered and negative-edge triggered flip-flops in the same circuit

8. System considerations • Use edge-triggered flip-flops wherever possible • Avoid latches • Most common: Master-slave D

9. IN Q0 Q1 CLK0 CLK1 CLK0 clocks first flip-flop CLK1 clocks second flip-flop CLK1 should align with CLK0, but is delayed due to clock skew Original state: IN = 0, Q0 = 1, Q1 = 1 Next state: Q0 = 0, Q1 = 0 (should be Q1 = 1) Clock skew • Goal: Clock all flip-flops at the same time

10. Clock skew • Difficult to achieve in high-speed systems • Clock delays (wire, buffers) are comparable to logic delays • Tp > ThTp > Tskew + Th • If Tskew < 0, Tperiod + Tskew > Tp + Tsu

11. Asynchronous versus synchronous • Asynchronous • State changes occur when state inputs change • Feedback elements may be wires or delays • Synchronous • State changes occur synchronously • Feedback elements are clocked

12. Asynchronous inputs • Clocked circuits are synchronous • Circuit changes state only at clock edges • Signals (voltages) settle in-between clock edges • Unclocked circuits or signals are asynchronous • No master clock • Real-world inputs (e.g. a keypress) are asynchronous

13. Asynchronous inputs • Synchronous circuits have asynchronous inputs • Reset signal, memory wait, user input, etc. • Inputs can change at any time • We must synchronize the input to our clock • Inputs will violate flip-flop setup/hold times

14. Synchronizer failure • Occurs when FF input changes near clock edge • Input is neither 1 or 0 when clock goes high • Output may be neither 0 or 1 • May stay undefined for a long time • Undefined state is called metastability

15. D CLK Q logic 0 logic 1 Synchronizer failure

16. asynchronous input synchronized input D Q Q D Clk Minimizing synchronizer failure • Failure probability can never be zero • Cascade two (or more) flip-flops • Effectively synchronizes twice • Both would have to fail for system to fail

17. Synchronizer Async Q0 Async Q0 D Q D Q D Q Input Input Clock Clock Q1 Q1 D Q D Q Clock Clock Handling asynchronous inputs • Never fan-out asynchronous inputs • Synchronize at circuit boundary • Fan-out synchronized signal

18. Summary • For sequential logic circuits, timing issues have to be considered. • Inputs are often asynchronous and can cause problems. • Different amount of delay at different part of the circuit can cause problems also. • Solutions: • Cascade flip flops in series • Design to keep timing alignment in mind (length of wires, etc)