XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing

1. XFEL 2D Pixel Clock and Control System XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing

2. OUTLINE • June meeting at DESY • C&C Hardware structure • C&C Firmware structure • Current Status • Outstanding Issues • Future plans

3. June Meeting at DESY • June meeting at DESY on XFEL and Petra3 • Meeting with K. Rehlich’s team • The structure for the TR board – capabilities • Supplied signals • XTCA backplane signals – P2P clocks and bussed LVDS signals • XTCA crate structure – How many boards can be supported • Meeting with P. Vetrov • DAMC2 card structure – capabilities • Designed for XTCA • The FPGA and the clock network • MLVDS transceivers • TCLKA and B reception into the clock network – Driving capability doesn’t exist • RTM connections – 54 differential pairs + 1 dedicated differential clock line • FMC connections – If needed for extra functionality • Availability

4. June meeting at DESY • Meeting with Petra3 team • Petra Bunch Uhr (PBU) unit • Interfacing PBU with the TR and CC boards • Timing • Start, Bunch Clock, Laser inputs + Spare • Signaling types (NIM/TTL) • Conclusions from the meetings • TR card will provide clocks and triggers to CC over the XTCA backplane • XTCA backplane sufficient for CC functionality • Bunch clock (4.5 MHz) and 99 MHz clocks will be provided on low-jitter, P2P lines (TCLKA/B) • DAMC2 can be used as a base for CC card • A custom RTM can be designed for CC master and slave functionality

5. CC hardware structure • Overall timing crate structure

6. CC Hardware Structure • Detailed CC connections Crate Layout

7. CC Hardware Structure • DAMC2 + custom RTM • Bunch clock on TCLKA, 99 MHz clock on TCLKB from TR • Jitter <= 100 psec • On-board oscillator + PLL for standalone testing • The CC master/slave (1 DAMC2 + RTM) capable of driving a 1 Mpixel 2D detector (16 channels per RTM)

8. CC Hardware Structure • Bussed LVDS lines utilised on xTCA backplane • From the TR • RX17 , TX17, RX18, TX18 • From the CC • RX19, TX19, RX20, TX20 • The CC will use the TR to synchronise to the following when used with non-XFEL sources • External Clock • External Trigger • Laser Clock • Spare • Telegram data content from TR • Start Train, Train Number, End Train, Bunch Pattern Index, DAQ Ready

9. CC Hardware Structure MCH TCLKA Bunch Clock FEE Clock (99MHz) TCLKB Trig (Start) RX17 Telegram Data TX17 Telegram Clock Timing Receiver RX18 CC Master CC Slave Reset TX18 Spare RX19 TX19 Command Ext Clock RX20 Veto Ext Trig TX20 Status = Signal Source • Telegrams are to be sent as a data and strobe/clock pair from the TR • Planned capability for the CC to generate 99 MHz clock and distribute on TCLKB

10. CC Firmware Structure • C&C firmware structure

11. Current Status • Just received the XUPV5 development board • Virtex 5 LX110T FPGA on board • Various clock sources • Differential and single-ended expansion headers • Going to use XUPV5 for firmware prototyping • Until DAMC2, TR, xTCA crate available • Daughter card designs for initial testing (our firmware and hardware) ready • 2 different versions • Version A – simple I/O functionality – Transmit/Receive on the same card • Will provide basic test functionality for FEEs • FPGA generated 99 MHz clock / 1 channel output • Version B – simple I/O + standalone clock generation + TR interface • Will provide the same functionality as DAMC2 + RTM • Limited number of channels (1 proposed) • Production will depend on the availability of DAMC2 / FEE needs

12. Current Status • Trying to arrange EDA tool usage with RAL • Cadence Allegro design flow • Telegram data protocol • Suggesting a protocol similar to the FAST commands • E.g. Start word + Payload + CRC • Daughter card designs • Version A • Suitable for basic testing FEE functionality • - 1 channel output only • - Clock not in spec but close (jitter, freq.) • - Trigger generated by firmware • (external trigger may be possible)

13. Current Status • C&C firmware • Fast Message Generation – Start and Stop messages

14. Outstanding Issues • Telegram data protocol should be finalised • Exact type of inputs to the TR – standard signals to the CC for non-XFEL sources • Next version of DAMC2 – changes to TCLKA/B according to CC requirements • Bi-directional TCLKA/B • RTM design considerations • Specs needed – Size, connector etc. • How to support IPMI • Power supply circuitry • Any other • DAMC2 availability and FEE requirements • Will determine the development of either RTM or daughter card B

15. Future Plans • Getting the daughter card ready • Firmware development • Initial in-house testing • Expecting DAMC2 • Getting RTM specs • RTM design

16. Schedule • Daughter card A schematic capture, layout • Daughter card A production • Firmware development • Initial tests with the development platform • RTM design/schematic capture • RTM layout • Tests with the DAMC2 + RTM September 2010 September - October 2010 September - October 2010 October 2010 October 2010 October – November 2010 November – December 2010 Depends on DAMC2 + crate availability – otherwise daughter card B development Supplying for FEE testing?

17. A -1 IDC-1/A 8 7 U14+U15 Ext. Veto In 6 3 A-C Coupler Status U9+U10 2x DS90LV001 5 4 T.R. Start In U13 8 7 U8 Veto EuroQuartz XOPL91050UCTA U1 DS90LV001 X-TAL 9.0278 MHz U12 5 4 Start / Reset U7 U2 : 2 74LVT74 DS90LV001 Delay U16 RJ45 DS90LV048A In-B Clk-2 U11 Clk-1 2 1 J3 ( Optional ) 2 1 U4 U5 In-A T.R. Clock In U3 U6 Clock 4.51MHz 99MHz Clk-2 Clk-3 DS90LV027A Clk-4 Shield Shield ICS581G-02LF MUX-PLL ICS527R-01LF Mult. PLL 0R 0R RJ45 RJ45 +3v3 J1 J2 SW-1 Force X-Tal

18. A-2

19. A-3