Matt Warren Valeria Bartsch, Martin Postranecky, Matthew Wing (and Alexey Lyapin, Bino Maiheu)

1. HEP Group Meeting September 2008ILC/CALICE (DAQ)ILC: International Linear Collider CALICE: Calorimetry for ILCDAQ: Data Acquisition Matt Warren Valeria Bartsch, Martin Postranecky, Matthew Wing (and Alexey Lyapin,Bino Maiheu)

2. ILC/CALICE DAQ People Accelerator Guys Post-Doc Alexey Lyapin Post-Doc Bino Maiheu Boss Matthew Wing Post-Doc Valeria Bartsch Engineer Martin Postranecky Engineer Me Group Meeting - ILC/CALICE DAQ - Matt Warren

3. Linear Collider (not a circle) • The plan is to build an new machine after the LHC. • 2020 (ish) • Detector development has already started • We need to get the data now as for testing, calibration and optimisation. • UCL are involved in calorimeter (CALICE) DAQ. ILC – a line! LHC – a circle! Group Meeting - ILC/CALICE DAQ - Matt Warren

4. 5 Hz / ILC vs LHC: Beam structure • LHC has collisions every 25ns (40MHz) 25ns • ILC (or CLIC) have periodic ‘Bunch Trains’ with long gaps between. Bunch Train // / 1% 99% Buffer data • Triggerless data readout Group Meeting - ILC/CALICE DAQ - Matt Warren

5. ILC vs LHC: Trigger(less) • LHC modules store event data for each beam-crossing (BX) • External system decides which data to keep – sends ‘trigger’ • Module “reads-out” • DAQ expects data DAQ pipeline Trigger • ILC wants to data from every BX • To reduce readout volume front-end modules decide what to keep: auto-trigger. • Data is stored until end of train and read/SENT out in the gap. • DAQ expects only blocks of data for each train memory DAQ Group Meeting - ILC/CALICE DAQ - Matt Warren

6. DAQ Concept • Building for multiple ILC CAL sub-detector prototypes • Generic DAQ for many (economies of scale) • Modular/Generic Structure: • Generic readout system as much as possible • Detector specific interfaces only at ends of chain • Other ‘bespoke’ functionality in FPGA with custom firmware • Commercial components and protocols where possible • Readout links use standard connectors and protocols • Currently on PCs with PCIe cards • Future could be use telecoms standard ATCA (or uTCA) crates • Use something “off-the-shelf” … DOOCs Group Meeting - ILC/CALICE DAQ - Matt Warren

7. DIF DIF DIF DIF Detector Unit Detector Unit Detector Unit Detector Unit Storage DAQ architecture UCL Detector Unit: ASICs DIF: Detector InterFace connects Generic DAQ and services LDA: Link/Data Aggregator – fanout/in DIFs and drives link to ODR ODR: Off Detector Receiver – PC interface for system. CCC: Clock & Control Card: Fanout to ODRs (or LDAs) CONTROL PC: DOOCS GUI (run-control) DAQ PC ODR LDA Control PC (DOOCS) CCC LDA DAQ PC ODR Group Meeting - ILC/CALICE DAQ - Matt Warren

8. ODR Hardware • Using development board that suits our needs well: • Based on Xilinx Virtex 4 FX100 FPGA (huge + 2xCPU) • We co-develop firmware with RHUL in VHDL • Receives data on 4 1.25Gb fibre optic receivers • Can write data to RAM at 600MB/s, to disk at 170MB/s • 4x 2.5 Gbit • 4 more via plug-ins • 128 MByte RAM • 8 lane PCI-Express Group Meeting - ILC/CALICE DAQ - Matt Warren

9. Clock & Control Custom Hardware SMAs (vertical) HDMIs LEMO (NIM) CPLD Debug Header RS232 Add-ons interface Group Meeting - ILC/CALICE DAQ - Matt Warren

10. Future ideas: ATCA • ATCA is a telecoms standard • Cards communicate using an array of links provided by the backplane • Backplanes have HUB slots • Point-to-point links from all other slots • Global clock links, config links. • ATCA cards can host Mezzanines (AMC) – “AODR” • μTCA is a crate for AMCs • Useful for debugging Group Meeting - ILC/CALICE DAQ - Matt Warren

11. Conclusion/Future plans • Beyond halfway through, but much to deliver: • Testbeam next year (or 2010) – we need to demonstrate this system works • ODR works now, but plenty of room to improve • Software growing • Planning for phase 2 • Even more generic (looking at SLHC work) • Use TCA Group Meeting - ILC/CALICE DAQ - Matt Warren