FPGA

1. Observer Controller FPGA software model Klaus WaldschmidtJohann Wolfgang Goethe-UniversityTechnische InformatikFrankfurt/Main, Germanywaldsch@ti.informatik.uni-frankfurt.de • Research Interests: • - Computer Architecture • Multicore Systems • Embedded System Design • Current projekt: • SDVM: Self Distributing Virtual Machine • for Multicore FPGA Observer Controller Reconfigurable system Input Output FPGA Environment In Out Environment

2. One or more processors support the intelligence which is necessary for the smart behaviour. • Things that think, a definition originally presented by MIT. • Embedded systems are more a or less networked systems. In consequence an Internet of things • exists additionally to the wellknow Internet of information Slide 2 Klaus Waldschmidt – Dagstuhl April ’08

3. Observer Controller System-specification Reconfigurable system Hardware/Software-partitioning Input Output Hardwaresynthesis Communicationsynthesis Software- compilation Environment Embedded systems and System-on-chips • Modern System-on-chips become more and more complex • Time to market becomes more and more a necessity • Robustness and trust in electronic systems is a big challenge in future • Power reduction for mobile applicationsbecome more and more important A parallel, flexible, scalable, and generic architecture will be required in future. Slide 3 Klaus Waldschmidt – Dagstuhl April ’08

4. Observer Controller FPGA software model Observer Controller Reconfigurable system Input Output FPGA In Out Environment Environment Slide 4 Klaus Waldschmidt – Dagstuhl April ’08

5. Multi-core FPGA (MP-SoC) • Multi-core FPGAs create a new kind of system realization… • …but there are still a lot of problems to solve: Reliability • Performance:Algorithms and programming (software) model • Reliability:Increase of lifespan and robustness • Flexibility for adaptivity and self-organization • Power management:Energy reduction for mobility Reliability,Flexibility and Power- Management Perform- ance Flexibility Power Manage- ment Slide 5 Klaus Waldschmidt – Dagstuhl April ’08

6. parallelcomputing self-organization reconfigurable (dynamic)computing adaptivecomputing Autonomous and organic behaviour of multi-core computing systems Slide 6 Klaus Waldschmidt – Dagstuhl April ’08

7. Multi-core Systems based on FPGA M M M M M M M M M M M M M M M M M M M M M P P P P P P P P P P P P P P P P P P P P P R R R R R R R R R R R R R R R R R R R R R FPGA • unite several PEs to form a parallel system f1 • increase number of PEs if needed • use available space on the FPGA f2 fy • implement special functionality on the FPGA • reconfigure at runtime fx What we need is a software model for FPGAs to make these features manageable. f3 fy Processing element (PE) Custom HWfunction FPGA Slide 7 Klaus Waldschmidt – Dagstuhl April ’08

8. The Self Distributing Virtual Machine (SDVM) ? HW type X M M fy P P R R Sites can join … Sites can join and leave the cluster without disturbing the execution Application to be run on heterogeneous, distributed hardware The SDVM is a virtualization of a parallel, adaptive, and heterogeneous cluster. The SDVM as a middleware between application and hardware Application runs transparently distributed on several sites application site SDVM SDVMlayer layer SDVM layer application application ? ? Core type A Core type B FPGA Network on chip (NoC) (bus, mesh, crossbar, Clos Net, …) Slide 8 Klaus Waldschmidt – Dagstuhl April ’08

9. params params params params params params params params memory memory memory processor processor processor reconfhardware reconfhardware reconfhardware site site site Working principle of the SDVM SDVM uses the dataflow principle to automatically distribute applications and data sites may vanish (data is pushed out before) code is needed at execution time only and thus the params are moved separately code fragments can be dynamically subsituted by configware SDVM features (virtual) global shared memory using COMA principle SDVM features distributed dynamic scheduling (work stealing principle) or join (new sites automatically ask for work) at runtime code code execute … execute … configware code code shutdown! FPGA NoC (bus, mesh, crossbar, Clos Net, …) Slide 9 Klaus Waldschmidt – Dagstuhl April ’08

10. System-Virtualization using the SDVM 1. FPGAs allow for parallel systems: multiple hardcores multiple softcores multiple custom function units 2. FPGAs allow for heterogeneous systems: PowerPC hardcore MicroBlaze softcore custom function units 3. Runtime-reconfigurable FPGAs make dynamic systems possible. Application FPGA Core type A Core type B NoC M M M M M M M M M M M M M M P P P P P P P P P P P P P P R R R R R R R R R R R R R R f2 SDVMR SDVM f1 The adapted SDVMR will act as a virtual layerfor dynamic reconfigurable Multi-Core FPGAs. Slide 10 Klaus Waldschmidt – Dagstuhl April ’08

11. SDVMR Objectives Combine all PEs on the FPGA to create a parallel system. Provide task mobility between all PEs even if they are heterogeneous. Virtualize the I/O-system to enable the execution of a task on an arbitrary PE. Combine the distributed memory of each PE to form a virtually shared memory. Manage the reconfiguration of the FPGA. Adjust the number of active PEs at runtime. Hide the actual number of PEs from the application to ease programming. Provide dynamic scheduling as well as code and data distribution. These features will be provided by the SDVMR software layer. Slide 11 Klaus Waldschmidt – Dagstuhl April ’08

12. Implementation architecture SDVMR site SDVMR site custom function unit fy custom function unit fy MicroBlaze Softcore MicroBlaze Softcore M M P P R R FPGA SDVMR site SDVMR site PowerPCHardcore M P R NoC (bus, mesh, crossbar, Clos Net, …) • The SDVMR is implemented as software running on each core. • Each core forms an independent site of the SDVMR cluster. • Custom function units will get attached to a core. • Custom function units as independent sites are planned. Slide 12 Klaus Waldschmidt – Dagstuhl April ’08

13. Partial reconfiguration custom function unit fz custom function unit fy PowerPCHardcore M P R MicroBlaze Softcore MicroBlaze Softcore Softcoretype B Softcoretype A M M M M P P P P R R R R FPGA SDVMR site SDVMR site SDVMR site SDVMR site NoC (bus, mesh, crossbar, Clos Net, …) • Reconfiguring a site: • The site to reconfigure drops out of the cluster • Some other site controls the partial reconfiguration of the FPGA • The SDVMR layer is started on the new softcore • The new site joins the cluster Custom function units can be reconfigured without changing the number of sites Slide 13 Klaus Waldschmidt – Dagstuhl April ’08

14. Site 1 Site 3 Site 2 Site 4 Test bench core 2 core 1 core 3 core 4 SDVM Ethernet • Each site simulates one core of the multi-core chip • Cluster consisting of four equal Intel PCs Slide 14 Klaus Waldschmidt – Dagstuhl April ’08

15. ? possible EM-state transitions due to workload variation HFM HFM HFM LFM HFM OFF LFM LFM The dynamic scheduling and workload distribution offers newdegrees of freedom when choosing an energy management policy. Ü LFM LFM OFF OFF SLEEP LFM OFF OFF Another application: Energy Management – cont‘d • The parallelism of most applicationschanges dynamically. • The SDVM features: • Autonomous scaling • Dynamic workload distribution • Distributed dynamic scheduling Slide 15 Klaus Waldschmidt – Dagstuhl April ’08

16. Conclusion The SDVMR… is a virtualization layer for dynamic reconfigurable FPGAs separates the application from the number and type of cores exploits the parallelism and dynamic features of todays FPGAs For further information visit the SDVM´s homepage at http://sdvm.ti.cs.uni-frankfurt.de Slide 16 Klaus Waldschmidt – Dagstuhl April ’08

17. Thank you for your attention! Slide 17 Klaus Waldschmidt – Dagstuhl April ’08