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Speed/Performance. Overview. Basic Delay Model and Components Sample Delays Examples from different families Hard-wired Structures Routing Arithmetic Logic. Antifuse Delay Model. Note: These numbers are approximate and work on better numbers is in progress.
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Overview • Basic Delay Model and Components • Sample Delays • Examples from different families • Hard-wired Structures • Routing • Arithmetic Logic
Note: These numbers are approximate and work on better numbers is in progress. UTMC, for PAL and PROM, has about 8 to 10 fF.
Hardwired Structures (1)Actel Routing Model Direct Connect Fast Connect (ns) (ns) RT54SX-1 0.2 1.1 RT54SXS-1 0.1 0.4
Hardwired Structures (2) XQR4000XL-3 Carry Logic CLB Fast Carry Logic (max) TOPCY Operand inputs (F1, F2, G1, G4) to COUT 2.7 ns TASCY Add/subtract input (F3) to COUT 3.3 ns TINCY Initialization inputs (F1, F3) to COUT 2.0 ns TSUM CIN through function generators to X/Y outputs 2.8 ns TBYP CIN to COUT, bypass function generators 0.26 ns TNET Carry net delay, COUT to CIN 0.32 ns Note: Always use extracted values for real circuits.
Hardwired Structures (3)Virtex-4 Carry Logic Notes 1. Values on rad-hard data sheet not available 2. Always use extracted values for real circuits TBYP (CIN to COUT): 200 ps, max