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CHAPTER 1

CHAPTER 1 . FLIP FLOP By : Pn Siti Nor Diana Ismail. Sequential logic Astable Monostable Bistable No stable state - 1 stable state - 2 stable states

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CHAPTER 1

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  1. CHAPTER 1 FLIP FLOP By : Pn Siti Nor Diana Ismail

  2. Sequential logic Astable Monostable Bistable • No stable state - 1 stable state - 2 stable states • Use oscillator to - one shot control i. SET generate waveform timing single pulse when ii. RESET trigger - e.g : Flip-flops, latches

  3. An Introduction • Latches and Flip-flops (FF) are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. • Latches are bistable devices whose state normally depend on asynchronous input. • Edge triggered FFs are bistable devices which synchronous input whose state depend on the input only at trigerring transition of clock pulse.

  4. Latch vs Flip-Flop The basic difference between Latches & FFs: the way in which they are changed from one state to the another state.

  5. LATCH • A type of temporary storage devices. • Bistable devices or multivibrator. • Asynchronous devices • It has 3 types: i. Basic S-R latch, divide by 2 categories : - Active – HIGH input S-R latch - Active – LOW input S-R latch ii. Gated S-R latch iii. Gated D latch

  6. i. S-R latch • Active – HIGH input S-R latch • Form with 2 cross coupled NOR Gated (a)Logic diagram (b)Logic symbol

  7. Truth Table for Active-HIGH input S-R latch

  8. Active – LOW input S-R latch • Form with 2 cross coupled NAND Gated (a)Logic diagram (b)Logic symbol

  9. Truth table for Active-LOW input S-R latch

  10. Example : Active – LOW input S-R latch Normally, when Q is HIGH, Q’ is LOW, The output of latch are always compliment each other

  11. Assignment 1 • Draw the output waveform for the Active High input SR Latch in diagram below

  12. ii. Gated S-R latch • It requires an enable input, EN • OPERATION : i. S-R control the state, when EN is high ii. Latch will not change until EN is high iii. When it remains HIGH, output will control by S-R input iv. Invalid state happen when S-R are simultaneously HIGH

  13. Truth table for Gated S-R latch S R G/EN Q Q’ 0 0 0 Q Q’ hold 1 0 0 Q Q’ hold 0 1 0 Q Q’ hold 1 1 0 Q Q’ hold 0 0 1 Q Q’ no change 1 0 1 1 0 set 0 1 1 0 1 reset 1 1 1 0 0 not allowed

  14. Example : Gated S-R latch

  15. iii. Gated D latch • Its only has one input • The input is called data input (D) • OPERATION : i. D is HIGH, EN is HIGH, latch will SET ii. D is LOW, EN is HIGH, latch will RESET The output Q is follow the input D, when EN is HIGH

  16. Truth table for Gated D latch D G/EN Q Q’ 0 0 Q Q’ hold (NC) 1 0 Q Q’ hold (NC) 0 1 0 1 Reset 1 1 1 0 Set

  17. Example : Gated D latch • The output follows the input when the gate is high but is in a hold • when the gate is low. • ~ En=high ‘1’, Q output will reset/set depend on D input. • ~ En=low ‘0’, Q output will hold condition.

  18. Flip-flop (FF) • It is a synchronous bi-stable devices. • edge-triggered FFs, Pulse Trigger FF (master slave) • It has 3 types of edge-triggered FFs, i. J-K ii. S-R iii. D • OPERATION: Change state either at positive edge (rising edge) or negative edge (falling edge) of clock pulse, and sensitive to it input only at transition of CLK. • +ve edge-triggered has no bubble at input. • -ve edge-triggered has bubble at input. • to identify edge-triggered FF by check it small triangle inside the block at clock (C) input. (Dynamic indicator)

  19. 1 Clock signal 0 Clock Cycle Time Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock signals & Synchronous Sequential Circuit • A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

  20. What is +ve and –ve Edge trigger ??

  21. i.Edge trigger S-R Flip-flop • Assume positive edge-triggered FF is RESET. The output result Q’ is complement (1’s) of output Q. Logic symbol

  22. Example : S-R Flip-flop

  23. ii.Edge trigger D Flip-flop • A +ve edge trigger is form with S-R FF and inverter D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

  24. Example : D Flip-flop

  25. iii.Edge – trigger J-K Flip-flop • The edge-triggered J-K will only accept the J and K inputs during the active edge of the clock. • The small triangle on the clock input indicates that the device is edge-triggered. • A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.

  26. Truth table Edge trigger J-K Flip-flop J K CLK Q Q’ 0 0 Q0 Q0’ Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 Q0’ Q0 Toggle (opposite state)

  27. Example 1: Edge trigger J-K flip flop +ve edge trigger-rising clock pulse

  28. Example 2: Edge trigger J-K flip flop -ve edge trigger – failing clock pulse

  29. Pulse-trigger Flip-flop (Master slave ) • It constructed with two latches. • The master latch is loaded with the condition of the J-K inputswhile the clock is HIGH. When the clock goes LOW, the slave takes on the state of the master and the master is latched. • The master-slave is a level-triggered device. • The master-slave can interpret unwanted signals on the J-K inputs. *truth table are same with edge trigger except the way it clocked

  30. It composed two section; master and slave • Master section : A Gated latch • Slave section :A Gated latch with inverted clock and its control by the output of master section • Operation: • State is determined by input J-K at leading edge of clock pulse. (in Master section) • It transfer from Master to Slave section at trailing edge of clock pulse because the output of Master is applied to inputs of slave and the clock is inverted

  31. Basic logic diagram for J-K flip-flop

  32. FLIP-FLOP APPLICATIONS 3 general applications of Flip-flop are : • Parallel Data Storage • Frequency Division • Counter Application

  33. Parallel Data Storage • Store data from parallel lines in group of FF.(store data in group) • Operation is illustrated in Figure 8. OPERATION : • Using 4 FFs. • 4 parallel data lines is connected to the D input of FFs. • Clock inputs connected together. (triggered by a same clock) • Asynchronous reset inputs connected to a common CLR line. (initially reset all FFs)

  34. Figure 8

  35. Frequency Division • Use to reduce the frequency of a periodic waveform • Pulse apply to clock input, J-K toggle (J=K=1) • Q output is a square wave with one-half the frequency of clock input. • Change state each trigger clock. • Frequency division,

  36. Example 1 – A single FF J-K FF as a divide-by-2 device. Q is one-half the frequency of CLK. Output change on the +ve clock edge.(this is +ve edge trigger)

  37. Example 2 – Two FFs • Using 2 FFs. • QB depends on pulse QA

  38. Counter • -ve edge trigger J-K FF are used(Refer figure in example). • Both FF initially RESET • FF A toggle when –ve going transition. • QA clocks for QB • FF B toggle when QA makes HIGH LOW transition

  39. Example • Used to generate binary sequence.(00,01,10,11) • Two repetition are shown in figure below

  40. Next class Be prepared for next preliminary test : Counter

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