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From tens to millions of neurons

From tens to millions of neurons. How computer architecture can help. Paul Fox. Computer Architecture Group. What hinders the scaling of neural computation?. Neural Computation = Communication + Data Structures + Algorithms. But almost everybody ignores the first two!.

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From tens to millions of neurons

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  1. From tens to millions of neurons How computer architecture can help Paul Fox Computer Architecture Group

  2. What hinders the scaling of neural computation? Neural Computation = Communication + Data Structures + Algorithms But almost everybody ignores the first two!

  3. What is Computer Architecture? • Designing computer systems that are appropriate for their intended use • Relevant design points for neural computation are: • Memory hierarchy • Type and number of processors • Communication infrastructure Just the things that existing approaches don’t consider!

  4. Our approach • Bluehive system • Vast communication and memory resources • Reprogrammable hardware using FPGAS • Can explore different system designs and see what is most appropriate for neural computation

  5. Organisation of data for spiking neural networks

  6. First approach – Custom FPGA pipeline

  7. Running 256k Neurons

  8. First approach – Custom FPGA pipeline • Real-time performance for at least 256k neurons over 4 boards • Saturates memory bandwidth • Plenty of FPGA area left, so could use a more complex neuron model • But only if it doesn’t need more data • But time consuming and not really usable by non computer scientists Can we use more area to make something that is easier to program but still attains performance approaching the custom pipeline?

  9. Single scalar processor Data bus = any width Data bus = 256 bits Block RAM Block RAM DDR2 RAM (from 200MHz FPGA) Block RAM … One 32-bit transfer at a time Processor

  10. Multicore scalar processor Data bus = any width Data bus = 256 bits Block RAM Block RAM DDR2 RAM (from 200MHz FPGA) Block RAM … Ruins spatial locality Inter-processor communication needed … Processor Processor Processor

  11. Vector processor – many words at a time Data bus = any width Data bus = 256 bits Block RAM Block RAM DDR2 RAM (from 200MHz FPGA) Block RAM … Vector Processor

  12. Productivity vs. Performance 125 Izhikevich.c NIOS II Run time (s) Dual-core NIOS II+BlueVec Bluespec System Verilog IzhikevichVec.c NeuronSimulator/*.bsv 2 1 200 500 5k-10k Lines of code Vector version doesn’t have much more code than original code Massive performance improvement

  13. Example for LIF character recognition LIF.c LIFVec.c 324 lines of code 496 lines of code

  14. LIF simulator on FPGA running a Nengo model

  15. Conclusion • When designing a neural computation system you need to think about every part of the computation, not just the algorithm • Some form of vector processor is likely to be most appropriate Or write your model in NeuroML and let us do the hard work!

  16. Questions?

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