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Christophe : General questions and future developments.

Orsay Talks. Christophe : General questions and future developments. Dominique : Last measurements on the Wave Catcher board. Naïve questions/ remarks. We have two different systems to design for the PID. For the forward : Analog memories seem the only possible option to:

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Christophe : General questions and future developments.

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  1. Orsay Talks • Christophe : General questions and future developments. • Dominique : Last measurements on the Wave Catcher board. Christophe Beigbeder

  2. Naïve questions/ remarks • We have two different systems to design for the PID. • For the forward : Analog memories seem the only possible option to: • Reach the time resolution of 30 ps. • Associate the charge measurement. • Drawback : the trigger rate is relatively low ( readout ) but ok for us ? • For the Barrel : • Time resolution : ~100 ps for the electronics • Charge measurement foreseen for all the channels ? • Trigger rate compatible only with a TDC structure ? • Ongoing work on the MAPMT. Hope to have a setup in Orsay. • Could the two designs be the same ? • Pros and Cons could be listed. • What’s the urgency of making a choice ? Drawback of having high performance analog memories for the Barrel - Time and charge measurement naturally associated - Payload of the high resolution ( amount of data ) - Cost of having only one chip developed for the 2 solutions. Christophe Beigbeder

  3. Tests board at SLAC • If we want to keep these 2 options open, -> What do we want to test at SLAC ? • A possible design for the barrel based on the SNATS, before preparing a specific version of the chip based on the same principles • Design a simple board with limited requirements : few channels , no charge measurement. • A more complicated one, close to a first prototype ? • A board for the forward PID based on the SAM chip. • See Dominique’s talk => new results and performances. Christophe Beigbeder

  4. Time stamper vs TDC • TDC : time measured between a Start & a Stop • Time Stamper : absolute time measurement SuperNemo experiment: 2 events will be stamped  ∆t = t2- t1   t = √2 t1 t2 ∆t ∆t resolution degraded by a factor of √2 ∆t = t2- t1 Christophe Beigbeder

  5. Requirements Requirements for SuperNemo Calorimeter Time Measurements : • time resolution < 100ps RMS Requirements for SNATS : • SNATS résolution  time résolution / √2 70ps RMS LSB  200ps Christophe Beigbeder

  6. SNATS performance summary • Technology Process: AMS CMOS 0.35µm • Clock Frequency: 160MHz • Number of cells: 32 ( limited by the INL ) • Dynamic Range: 53 bits • 48 clock counter bits • 5 interpolator bits • Time coverage: 20 days • LSB = 250ps • DNL < 10% • Channels per chip = 16 • Dead time per channel : 400ns . 16 *400 per 16 channels • Production : shared run as for Babar. 67 Euros / chip based on a recent production of ~500 chips . • Not “ naturally “ protected against SEL. Test of the SNATS in beam as it has been done in LHCb and will be done for the upgrade. Christophe Beigbeder

  7. 64 Channels ? A very preliminary 16 channel test board synopsis USB2/1 - VME Need to be linked to The local Daq ? Firmware : what do we do When needed ? Early 2010 Christophe Beigbeder

  8. Next steps • Development of 2 setups for SLAC. • Development of a TDC for the barrel ? • Proposal for the integration of the PID electronics in ETD architecture. Christophe Beigbeder

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