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Status of the electronics and DAQ systems of the MEG experiment

This document provides an overview of the electronics and data acquisition systems used in the MEG experiment at INFN. It includes information on the various components, their installations, tests, and readiness status. The document also highlights the configuration, firmware, trigger tree, analysis software, and trigger lists.

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Status of the electronics and DAQ systems of the MEG experiment

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  1. Status of the electronics and DAQ systems of the MEG experiment

  2. INFN-Le HV 1:1 1:1 Active Splitter Active Splitter PSI 1:1 1:1 Trigger 216 4:1 4:1 Trigger front PMT atten Trigger LXe 630 lateral PMT 3 crates INFN-Pv HV DRS DRS 1:1 Active Splitter 60 120 DRS bars PMT Ramp 1:1 DRS 4:1 TC DRS HV DRS 8:1 APD Pre-Amp fibers 512 5 crates INFN-Ge INFN-Ge HV PSI Hit registers 32 Wires Pre-Amp 576 DC 1156 4 boards Strips Pre-Amp Aux. devices Electronic chain

  3. pE5 area ‘counting room’ Ancillary system INFN-Pi Trigger INFN-Pi Trigger clock start stop sync Trigger Trigger Start Front-End PCs Main DAQ PC PC (Linux) PC (Linux) PC (Linux) PC (Linux) Run start Run stop Trigger config PC (Linux) 3 crates PC (Linux) 20 MHz clock PC (Linux) Busy Error DRS PC (Linux) PSI DRS PC (Linux) PSI DRS DRS PC (Linux) DRS Event builder Hit registers PC (Linux) Gigabit Ethernet INFN-Ge Trigger signal Event number Trigger type PC (Linux) 5 crates PC (Linux) Type3 On-line farm storage INFN-Pi 1 crate DAQ and control

  4. HV system Active down regulation of an external HV supply 4 different requirements • Lxe: 1000V , 100 uA • TC bars: 2400V, 1 mA • TC curved: 500V, <1 uA • DC: 2400V, ~1 uA • 10 chn per board - 180 chn per crate • 24-bit ADCs for high accuracy (20mV) • Read out every 4 seconds of 900 chn Commercial HV suppliesinstalled Mass productioncompleted Installationcompleted in January ‘07 Tests • laboratory tests • 60 chn for TC ran stably for 2 weeks in December The system isready

  5. Splitter 4÷1 Trigger or DRS Inputs • Single coaxial cable (RG178–9m) • Negligible crosstalk 1÷1DRS output • high bandwidth • High density twisted pairs • crosstalk ~ 0.6% 1÷1trigger or Type3 output Standard twisted pairs cable Power

  6. SplitterSummary Splitter • 16 inputs • 16 output 1÷1 differential 400 MHz • 16 output 1÷1 differential 100 MHz • 4 outputs 4÷1 attenuated differential 100 MHz • Noise <1 mV rms • Cross-talk ~0.6% with LXe signals • Common calibration levels from backplane Installation • Completed in September 06 Cables • All cables ready at PSI • Only TC cables installed during December 06 run Test • Satisfactory test during December 06 run The system isready

  7. TC APD-preamplifiers APD pre amplifiers • First prototype with problems on IC and cross talk • Second prototype design and test completed • Mass production and test completed • Assembly and test completed • System delivery in Aug ’07(Glued to the TC fibers)

  8. TC APD hit registers • Mezzanine board host on the PSI GP-VME boards (the same boards used for DRS) • Design, production and test completed • The system consists of 6 VME boards • System delivery Aug ‘07 (with the detector)

  9. TC Ramp PMT ramp generator • Design of the final boards completed • Mass production in progress • system delivery 8 boards Aug 07

  10. Type2 Front end Ancill Type1 TriggerBoards

  11. Trigger system status Installation • The entire system has been installed in Jul 06. • Active sub-detectors cabled in Nov 06 • Pedestal and TC triggers provided during Dec 06 test run • Integration of the trigger and DAQ Nov-Dec 06 The system is ready Configuration firmware • Baseline Version 3 ready for download Jul 07 • Scaler readout (implemented for Type 1.3 @Run06) • Memory space arrangement (faster read-out) • Revised trigger list Trigger tree • Increased number DCH wire sum (individual inputs for each end) • Cosmic ray counters Analysis software • Base analysis tools available • Trigger parameters evaluation and download, under development • Monitoring and efficiencyevaluation tools

  12. 14 boards . . . Type2 Type2 Type2 Type2 Type2 Type2 14x 48 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 4 4 4 4 16 16 16 16 16 16 16 16 The trigger tree 2 boards LXe front face (216 PMTs) 2 x48 5+5+2 boards LXe lateral faces back (216 PMTs) 4 in 1 lat. (144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1 . . . 1 board 9 x 48 2 x48 1 board 9 boards . . . Timing counters curved (512APDs) 8 in 1 bars(30x2 PMTs) 9x 48 1 x48 1 board 4 boards Drift chambers 64 channels 4x 48 2x 48 Auxiliary devices 16 channels 2 x48 CR counters 32 channels

  13. Triggerlist (1) QTL QTH DWW DWN MeV LXe charge e+-g direction e+-g timing trig.# name conditions 0 MEGQSUM> QTH && D <DN && |T|<TWN 1 MEG-QQSUM>QTL && D <DN && |T|<TWN 2 MEG-DQSUM> QTH && D < DW && |T|<TWN 3 MEG-TQSUM> QTH && D <DN && |T|< TWW 4 RD-narrow QSUM> QTL && |T|<TWN 5 RD-wideQSUM> QTL && |T|<TWW

  14. Trigger list (2) trig.# name conditions 6 p0QSUM> QTH && QNaI > QN&& |T|<TWN 7 p0-NaIQSUM>QTL && |T|<TWN 8 NaIQNaI > QN 9 LXe-highQSUM> QTH 10 LXe-lowQSUM> QTL 11 CW QTL < QSUM< QTH 12 neutron Qpatch<QTpatch&& Qi< QTi 13 a pulse-shape && QSUM < QTL && QWIRE> QTWIRE 14 laser QLAS > QTLAS 15 led

  15. Trigger list (3) trig.# name conditions 16 michel NDC  4&&QL> QT&& QR > QT&& (QL+QR) > QTS 17 DC track out NDC  4&& Iout 18 DC track NDC  4 19 DC + CR single DC&& CR 20 DC 21 CR 22 TC QL> QT&& QR > QT&& (QL+QR) > QTS 31 pedestal internally generated random triggers

  16. Diff. driver Proces. Algor. FADC LVDS Tx Cyc. buff Cyc. buff Type1 FPGA Proces. Algor. Proces. Algor. LVDS Rx LVDS Rx LVDS Tx LVDS Tx Cyc. buff Cyc. buff Cyc. buff Cyc. buff Type2 Type2 FPGA FPGA Cyclic buffers Type1 layer Analog inputs Type2 layer Final Type2 Trigger output

  17. Monitoring: TRG Waveform • 512 channels (5120 ns) • 10 FADC bit data • Range 0 V --> 1V • 20 MHz Bandwidth T (ns) • Typical pulse 400 mV • Baseline Fluctuation  1 mV (s 0.4 mV) T (ns)

  18. Monitoring: system operation Periodic monitor of the system parameters performed automatically in the DAQ • Clock locking • Synchronous operation • LVDS data transmission • Computer busy • Rates (trigger, channel) Automatic alarms in case of failure

  19. Detector monitoring: rates Rate of individual channels (independent of trigger)

  20. Efficiency: tools • Cyclic buffers • dump-mode used to take 5us depth snapshot of the trigger status for monitoring, debugging and efficiency evaluation (PMT signals, physical quantities estimators: charge, time, amplitude, position, patterns …) • source-mode used to process simulated events as well real recorded events • Trigger • Prescaledunbiased triggers simultaneously acquired with meg events • Algorithm emulators • Simulation of FPGA algorithms with Xilinx tool intensively used • Emulation by means of c++ code in progress • Simulated data • Meg events • Calibration events

  21. DRS2 Mezzanine boards FPGA with 2 Power-PC PSI GVME Board

  22. DRS System Optical fiber Front-end PC Back-end PC Ethernet All channels equipped with DRS2 • 2636 channels • 1024 cells per channel • 0.5 - 2.5 GHz sampling speed • After calibration pedestal noise at 0.5 mV RMS Off-line cluster

  23. DRS2 online calibration The pedestal is dependent on the cell number • Need of individual pedestal value for each bin The non-linear response function depends on the cell number • Need of different response functions for each bin • Measure Vin – ADCout characteristics with precise DC power supply at the DRS2 input • Fit and store parameters online • Write on disc linearized, pedestal subtracted samples mV ADC counts / 10

  24. DRS3 status 50 prototypes of DRS3 available for test

  25. DRS3 linearity Uout (V) Uin (V)

  26. DRS3 nonlinearity 30 deg. C Point deviation from linear interpolation for five arbitrary cells • Integral nonlinearity is below 1mV with only one offset per cell used for correction • Output changes by ~1mV in 20 deg. C --> Tc = 50 ppm 50 deg. C

  27. DRS3 summary • No dangerous temperature instability • Readout speed increased 16 MHz (DRS2) -> 33 MHz • “Region Of Interest” – Readout mode works • Master clock signal (LVDS) can be digitized differentially  improvement in clock signal • Plan: • VME boards with DRS3 test in July 2007 • Order engineering run after all tests have been finished • Get chips in ~December, but not in time for this year’s beam time

  28. Auxiliary digitizer:Type3 Modified Type1 boards to produce an auxiliary digitization of the LXe signals

  29. Auxiliary digitizer status • Higher input capability(32 channels), no LVDS transmission • 612 PMTs on LXe lateral+back sides 20 boards • Prototype tests:Jan 07 • Bit-stream downloading through VME • Control signal (CLK, SYNC, START, STOP) distribution • FADC digitization and storage • RAM readout • Production:Apr 07 • Tests:May 07 • Installation:Aug 07

  30. DAQ 80 GB System Disk RAID 1 (Mirror) VME-Interface Front-End #1 80 GB System Disk RAID 1 (Mirror) VME-Interface Front-End #2 Gigabit Switch . . . NFS 80 GB System Disk RAID 1 (Mirror) SC-FE 1.2 TG Data Disk RAID 5 /home/meg Back-End

  31. Multi-threading model Calibration Thread Zero-copy ring buffers VME Round-Robin distribution Calibration Thread VME Transfer Thread Collector Thread Calibration Thread Network Calibration Thread

  32. DRS Readout rate Optimal readout rate of DRS full waveforms with 4 calibration threads: 30 events/s During Dec 06 run max readout at 7 events/s • Double event readout • Code optimization • Single calibration thread

  33. DRS Readout rate Assuming 50% occupancy Zero suppression done on the front-end Max transfer rate at 50 events/s • Hits the VME transfer speed Much larger than the expected maximum triggerrate of20 events/s

  34. Trigger readout rate • Type 3 boards (32 ch/board) • Standard 2EVME A32, D64 Readout • For 1 cycle TAS  650 ms/board( v  50 MB/s) • 20 boards/crate: 70 events/s  (%Live)  80% @ trigger rate = 20 s-1 • Type 1 (16 ch/board) & Type 2 (18 ch/boards) • Custom 2EVME A32, D32 Readout (no access to A31-A0 during data broadcast) • For 1 cycle TAS  1300 ms/board( v  25 MB/s) • 20 boards/crate: 60 events/s  (%Live)  75% @ trigger rate = 20 s-1

  35. Higher DAQ rate Higher rate is considered only for calibration events • 50 Hz full waveform readout hits VME transfer limit (83 MB/sec) • VME transfer size can be reduced by doing zero-suppression and ADC/TDC analysis on VME side • Use embedded Power-PC CPUs (C-code) • Use FPGA (VHDL-code) • Tools • Basic zero-suppression in VME in late 2007 • ADC/TDC analysis in VME later in summer, need input from sub-detector groups • Possibility of reaching 100 Hz

  36. DAQ rate vs. amount of data • DAQ speed is not a limiting factor • The total data size needs solution: • 30 Hz is maximal VME speed for full waveforms → >270 MB/sec • Data transmission limit is 20 MB/sec (=250TB/year)→ need online reduction10x • Storage limit is 30 TB/year→ need offline reduction8x

  37. Online data reduction The factor10 data size reduction obtained within the DAQ system: • Level 3 trigger in the Event Builder task: • Fast linear fit of the LXe energy with trigger wfms • Presence of an e+ with a minimal momentum using DC information • Waveform data compression • Zero suppression • ADC/TDC like data for calibration • Waveform rebinning

  38. Data size reduction Possible algorithms for data size reduction • Zero suppression: hit if max.ampl. > n x s(baseline) • Readout window at the trigger time • Pile-up flag: Zero-crossings of first derivation • Re-binning of signal tail4:1, 8:1 • ADC for calibration events: Numerical integration of signals over baseline 4 ns bins 0.5 ns bins

  39. Conclusions • Splitters: installed, operational, expected performances, test in Dec 06 • Fiber preamp: problem with an IC fixed, test passed, mounted on the TC detector, installation in Aug 07 • Hit registers: mezzanine boards produced, FPGA firmware ready (PSI GPVME board), installation in Aug 07 • Trigger: installed, operational, built-in debugging and control tool, need tuning after detector turn on, test in Dec 06

  40. Conclusions • DRS2: installed, operational, good for timing, temperature dependence, usable with DC • DRS3: prototype test phase, final solution, not available in 2007 • Aux digitizer: production problem solved, prototype test completed successfully, ready for 2007 run • DAQ: installed, operational, good performances, test in Dec 06 run The electronics and the DAQ systems are expected to be ready for the 2007 run

  41. Rack space

  42. Trigger reminder trigger observables • energy, direction and time (Lxe calorimeter) • e+time and approx. direction (Timing Counters) Digital approach • Flash analog-to-digital converters (FADC) • Field programmable gate array (FPGA) Expected rate • For 108 muon stop rate

  43. Triggerfeatures All triggers can be: • masked • prescaled(up to 32 bits) Other information Type 1 • 100 MHz, 5 s depth, 10 bits,waveforms for all channels • Single rate for each channel Type 2 • Rate for each trigger type • Event Counter (hardware distributed to the DRS boards) • Trigger pattern (hardware distributed to the DRS boards) • Live Time and Dead Time

  44. Trigger efficiency: example low intensity (slit = 10%) high intensity (slit = 100%) ms ms events associated with the TRG STOP ( ~1ms delay) • Extract pulses for • “Trigger” events • “Unbiased” events (out of trigger window and with 10 mV threshold)

  45. Trigger efficiency:TC charge Secondary particles Unbiased Trigger rescaled by RpulseT Landau peak for e+  = NT/NU Interpolation by erf function Npe  almost full efficiency at Landau peak(~6MeV, ~500pe)

  46. Rotating 0.2-1 ns Inverter (“Domino”) chain signal Input 1 Output 1 Input 2 Analog output Analog switch Channels 3 to 10 16 MHz DRS2 primer Need of external buffer and FADC

  47. DRS2 Temperature Dependence Tc ~ 1.4 % / ºC Vout [V] T [º C] DRS2 has a marked dependence on the temperature

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