CS 7960-4 Lecture 17

1. CS 7960-4 Lecture 17 Reducing Power with Dynamic Critical Path Information J.S. Seng, E.S. Tune, D.M. Tullsen Proceedings of MICRO-34 December 2001

2. Instruction Criticality • Blue instructions are critical • Yellow instructions are non-critical • -- they can be slowed without • increasing execution time • The critical path can change • Critical instructions are usually • executed in order

3. Criticality Metrics • QOLD – instructions that are the oldest in the • issueq are considered critical • can be extended to oldest-N • does not need a predictor • young instrs are possibly on mispredicted paths • young instruction latencies can be tolerated • older instrs are possibly holding up the window • older instructions have more dependents in the pipeline than younger instrs • long-latency instrs are probably on the critical path

4. Other Metrics • QOLDDEP: Producing instructions for oldest in q • ALOLD: Oldest instr in ROB • FREED-N: Instr completion frees up at least N • dependent instrs • Wake-Up: Instr completion triggers a chain of • wake-up operations • Instruction types: cache misses, branch mpreds, • and instructions that feed them

5. Slow FUs

6. Low Power Techniques • Slower circuit styles that consume less power • Smaller transistors consume less power, but take • longer to charge their load • Higher threshold voltage reduces leakage and • increases delay • Assumption: Leakage accounts for 10% of the • base; low power FUs consume 80% less dynamic • power and 50% less leakage

7. IPC to FU-Power Ratio • Approximates hot-spot evaluation • Number of thermal emergencies might be a better metric • Total-IPC/Total-Power is more suitable for power delivery and battery • life evaluations

8. Serial Nature of Critical Instrs

9. Issue Queues and Criticality

10. Proposed Microarchitecture Criticality Predictor In-order issueq FUs Dispatch o-o-o issueq FUs FUs FUs FUs FUs • Imbalance between the two queues can worsen performance • Favorable implications for temperature • o-o-o issueq can have long latency • Criticality predictor is likely to not be a hot spot

11. Overall Results

12. Power-Aware Architectures • Speculation control • Criticality • Leakage control by de-activating structures • Dynamic voltage and frequency scaling • Metrics: temperature, peak power, battery life, • packaging costs, power delivery, etc.

13. Next Class’ Paper • “Simultaneous Multithreading: Maximizing On-Chip • Parallelism”, D.M. Tullsen, S.J. Eggers, H.M. Levy, • Proceedings of ISCA-22, June 1995

14. Title • Bullet