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CS 140L Lecture 4

CS 140L Lecture 4. Professor CK Cheng 4/22/02. Libraries Guide. D. FDCE. Asynchronous Clear. Q. Inputs Output. CE. C. CLR CE D C Q 1 X X X 0 0 0 X X No change 0 1 1 1 0 1 0 0. CLR. Clock Enable.

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CS 140L Lecture 4

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  1. CS 140L Lecture 4 Professor CK Cheng 4/22/02

  2. Libraries Guide D FDCE Asynchronous Clear Q Inputs Output CE C CLR CE D C Q 1 X X X 0 0 0 X X No change 0 1 1 1 0 1 0 0 CLR Clock Enable CLK = 1 CLK = 0

  3. Q D CLK CLK tsetup thold t D t Q t tpcQ

  4. 3 bit shift register B D C A Q Q Q D D D CLK Time Steps A B C D • 0 0 X X X • 1 0 X X • 2 0 1 0 X • 1 0 1 0 • 1 1 0 1 • 0 1 1 0 • 0 0 1 1 • 1 0 0 1

  5. 3 bit counter (asynchronous) A B C Q Q Q D D D CLK CLK t CLK 1 0 1 0 t CLK 1 1 0 0 t CLK 1 1 1 1 t 7 6 5 4

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