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FPGA Implementations for Volterra DFEs

FPGA Implementations for Volterra DFEs. Andreas Emeretlis George Theodoridis. Outline. Volterra Decision Feedback Equalizers Hardware Architecture Implementation Considerations Experimental Results and Comparisons Conclusions. Electronic Equalization in Optical Systems.

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FPGA Implementations for Volterra DFEs

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  1. FPGA Implementations for Volterra DFEs Andreas Emeretlis George Theodoridis

  2. PCI 2014 Outline • Volterra Decision Feedback Equalizers • Hardware Architecture • Implementation Considerations • Experimental Results and Comparisons • Conclusions

  3. PCI 2014 Electronic Equalization in Optical Systems • Limited capacity of optical fibers • Channel impairements • Chromatic Dispersion (CD) • Polarization Mode Dispersion (PMD) • Reduction of costly optical equalization • Implementation of complex DSP algorithms Intersymbol Interference (ISI)

  4. PCI 2014 Decision Feedback Equalizer (DFE) • General Form: • Feed-Forward Filter (FFF) • Pre-cursor ISI • Feedback filter (FBF) • Post-cursor ISI • Quantizer • Symbol Decision • Adder • Implementation challenges • Pipelining the feedback loop • Parallelism of quantizer loop • Non-linear filters • Increased complexity • Hardware resources

  5. PCI 2014 Linear vs Non-linear DFEs Linear DFEs Non-linear DFEs

  6. PCI 2014 Volterra Decision Feedback Equalizer • Direct Detection  Non-linear distortion • 2nd order Volterra filters (VDFE) • Sensitivity to sampling phase • Fractional Spacing  Processing of 2 samples/symbol

  7. PCI 2014 Outline • Volterra Decision Feedback Equalizers • Hardware Architecture • Implementation Considerations • Experimental Results and Comparisons • Conclusions

  8. PCI 2014 Feed-forward Transformations • Parallelism • Unrolling the filter equation • Pipelining • Registers between filter elements • Synchronization registers

  9. PCI 2014 Feedback Transformations • Loop Precomputation • Computational units in the FF part • Multiplexer loop • Loop Pipelining • Lookahead • Loop Unrolling J0(n)=Î(n-1) Î(n-1) J1(n)=Î(n-1) Î(n-2) J2(n)=Î(n-1) Î(n-3)

  10. PCI 2014 Feedback Architectures – Area Reduction Straightforward Approach Incremental Processing Approach L-3 stages N L L-2 stages L-1 stages L-1 stages L-N

  11. PCI 2014 Outline • Volterra Decision Feedback Equalizers • Hardware Architecture • Implementation Considerations • Experimental Results and Comparisons • Conclusions

  12. PCI 2014 Employed FPGA Platform (1/2) • Configurable Logic Architecture • Configurable Logic Blocks (CLB) • CLBs are interconnected via Switch Matrix • CLB  2 Slices • Slice  4 Look-Up-Tables, Carry Computation Chain, 8 Flip-Flops • Drawbacks • Predefined geometry • High routing delay • No 100% occupation of each slice

  13. PCI 2014 Employed FPGA Platform (2/2) • Hardcore DSP Logic Architecture • On-chip hardwired modules • Low area occupation • High-speed implementation of DSP algorithms • Dedicated high-speed interconnection resources • DSP48E1 Slice • 25 × 18 bits multiplier • 48 bits accumulator • Bypass multiplexers • SIMD adder • Internal pipeline registers • Cascading I/O ports

  14. PCI 2014 Implementation Considerations: Wordlength • Input: 7 bits • 6 bits fractional • Volterra inputs: 9 bits • 8 bits fractional • Coefficients: 13 bits • 12 bits fractional • Datapath: 14 bits • 13 bits fractional

  15. PCI 2014 Implementation Considerations • FIR filters • Pipelined Mul-Add modules • Adder cascades • Volterra Kernel • Pipelined standalone adders • Fabric interconnection of DSP slices • Pre-computation stage • Pipelined standalone adders • Manual SIMD mode (3 × 14 bits)

  16. PCI 2014 Outline • Volterra Decision Feedback Equalizers • Hardware Architecture • Implementation Considerations • Experimental Results and Comparisons • Conclusions

  17. PCI 2014 Experimental Results Straightforward Approach Incremental Processing Approach

  18. PCI 2014 Experimental Results: Performance Comparison Straightforward Approach Incremental Processing Approach

  19. PCI 2014 Experimental Results: DSP Utilization Comparison Straightforward Approach Incremental Processing Approach

  20. PCI 2014 Outline • Volterra Decision Feedback Equalizers • Hardware Architecture • Implementation Considerations • Experimental Results and Comparisons • Conclusions

  21. PCI 2014 Conclusions • Not predictable performance • Important progress of reconfigurable technology • Efficiency of hardwired modules • FPGA: suitable platform for high-speed communications • 10 Gb/s with ~50% of DSPs • 17 Gb/s with ~100% of DSPs

  22. PCI 2014 Thank you for your attentionQuestions?

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