FPGA Design for Preshower System Test

1. FPGA DesignforPreshower System Test Suresh Kumar LALWANI(BARC INDIA) Division EP/CME (Under Guidance of: Serge Reynaud) Preshower Collaboration Meeting, 28th Nov 2002

2. PRESHOWER SYSTEM TEST Block Diagram Mother Board Prototype Power LVDS MUX, PLL & CCU Control Path D O H From Last CCU 2.5V, 5VA, 5VD To Next CCU I2C SDDU x4 Isolators & LVDS Drivers G O H PACE Micro Module FPGA1 x4 ~100m ADC x4 PACE Micro Module FPGA2 G O H Isolators & LVDS Drivers SDDU x4 ~100m ADC Connector JTAG Programming and M16C Interface I2C JTAG Board 40MHz OSC JTAG M16C Module RS232 to PC Power Preshower Collaboration Meeting, 28th Nov 2002

3. Features Required in FPGA: - Interface to 2.5V and 5V CMOS devices - LVDS support & PLL - Sufficient Memory (49,920 bits for 10 Triggers@13 bits) - Sufficient Logic Gates (~100k) and I/Os - Suitable Package M16C x 4 5V CMOS 5V CMOS PACE ADC FPGA? 2.5V GOL 5V LVDS 2.5V, LVDS CCU/PLL Preshower Collaboration Meeting, 28th Nov 2002

4. Selected FPGA - Altera ACEX EP1K100QC208 Available Features: - Power Supply = 2.5V Available on board - 5V Tolerant Inputs/Outputs No need of external Level Translators - Memory bits 49,152 Sufficient to store 10 Trigger data@12bits - Package - 208pin PQFP Easy to Solder/De solder - Price - very low ~ USD 30.- Features Not Available: - LVDS support External LVDS devices required - PLL External Delay Lines required Preshower Collaboration Meeting, 28th Nov 2002

5. Selected FPGA Interfaced to Surrounding Devices : x 2 M16C Delay Line x 4 5V CMOS 5V CMOS PACE ADC FPGA EP1K100 2.5V GOL 5V L V D S LVDS LVDS 2.5V x 4 CCU/PLL Preshower Collaboration Meeting, 28th Nov 2002

6. Design Blocks implemented in FPGA: K-Chip Functions Data from 4 PACE/ADC To SDDU Reset from CCU To Delay Lines LV1 & Clock from PLL M U X To PACE Internal Signals Generation Trigger, ReSynch, CalPulse Design Blocks Developed Earlier for PACE2a Test MB Micro Controller (M16C) Interface To JTAG Board Preshower Collaboration Meeting, 28th Nov 2002

7. K- Chip Functions FIFO FIFO Write at 20MHz FIFO Read at 40MHz Data (12 bit) from ADC1 FIFO1 512x14bits Data Multiplex Data (12 bit) from ADC2 FIFO2 512x14bits Output Register Data to SDDU & M16 Interface Data (12 bit) from ADC3 FIFO3 512x14bits FE (15th bit) Data (12 bit) from ADC4 FIFO4 512x14bits Data Valid & Serial Address from all PACE Delay & Logic SrAdd to FIFO (13th bit) First slot to FIFO (14th bit) Write Request to FIFO From M16 Interface Readout Logic (Read Controller & Logic) To SDDU Input Sequence 100 101 110 111 Trigger Trigger Decoder ReSynch LV1 from PLL CalPulse BC0 Serial Data Delay Lines Programmer Reset Clock EN_MuxClk_DL EN_Calib_DL Preshower Collaboration Meeting, 28th Nov 2002

8. FPGA Design Features Compared with K : Extra Features Implemented(Not available in K) - Delay Lines ProgrammerRequired - Internal Signals Generation Helps Data Collection till CCU/PLL is Ready - M16C Interface Helps Data Collection till Driver & SDDU is Ready - SDDU Interface Data collection in SDDU till GOH is ready Features Not Implemented(But available in K) - I2C InterfaceShould Not Affect System Test - Error CheckingShould Not Affect System Test - Data formattingShould Not Affect System Test -GOL InterfaceNeeds to be implemented when GOH is available Preshower Collaboration Meeting, 28th Nov 2002

9. Conclusion : - FPGA Design coding has been completed (Using VHDL and Schematic design entry in Altera’s MaxPlusII), - The design has been simulated and is ready for testing, - Part of the design and the study done would be useful for future developments e.g. PACE3 Test Board and DDU. Preshower Collaboration Meeting, 28th Nov 2002

10. End Design details…..

11. K_FIFO FIFO Write at 20MHz (ADC Clock) FIFO Read at 40MHz (Master Clock) 12bit data from ADC1 FIFO1 512x14bits Data Multiplex 12bit data from ADC2 FIFO2 512x14bits Output Register Data to SDDU 12bit data from ADC3 FIFO3 512x14bits Selected FIFO Empty (15th bit) 12bit data from ADC4 FIFO4 512x14bits Select FIFO (from Readout Logic block) Read Request ( from Readout Logic block) Write Request & First Slot Generation logic Data Valid & Serial Address from all PACE Write Request to FIFO Serial Address to FIFO (13th bit) First slot to FIFO (14th bit) Preshower Collaboration Meeting, 28th Nov 2002

12. Readout Logic Trigger from Trigger Decoder Logic block AFULL generate & block Trigger Wait on Trigger Up Read Trigger Count Trigger to PACE Down Count=0 Ready From SDDU Read Controller Count 96 (1 Trigger Data) Enable Write Enable To SDDU TC MUX FIFO Empty Read Request MUX Select FIFO Select FIFO M16C Reads FIFO Read Request Signals from M16C Interface Logic block DEMUX Read Request to FIFO Select FIFO M16C Control Preshower Collaboration Meeting, 28th Nov 2002

13. Read Controller Reset =‘1’ M16C_Control_bar =‘0’ s0 M16C_Control_bar =‘1’ Reset_Out = ‘1’ FIFO_ No = 0 s1 Trig_Count_Zero =‘1’ s2 Trig_Count_Zero =‘0’ FIFO_Read Request = ’1’ Count_96_En = ‘1’ s3 Ready =‘0’ Ready =‘1’ s4 FIFO_Empty =‘1’ FIFO_Empty =‘1’ Ready =‘0’ FIFO_Empty =‘1’ s5 s6 Ready =‘0’ FIFO_Empty =‘0’ Ready =‘1’ s7 Count_96_TC =‘1’ s8 FIFO_No ++ FIFO_No != 0 FIFO_No = 0 s9 s10 Trig_Count_Dec = ‘1’ Preshower Collaboration Meeting, 28th Nov 2002

14. Trigger Decoder LVIN = ‘0’ Reset = ‘1’ s0 Trigger_Register(2) = ‘1’ if LVIN = ‘1’ LVIN = ‘1’ s1 Trigger_Register(1) = LVIN LVIN = ‘0’ LVIN = ‘1’ s2 Trigger_Register(0) = LVIN OutputTrigger_Register Value Trigger = ‘1’ 100 Synch_bar = ‘0’ 101 CALIB = ‘1’ 110 BC0 = ‘1’ 111 s3 Note: LVIN is nothing but T1 coming from PLL Preshower Collaboration Meeting, 28th Nov 2002

15. Delay Line Programmer Program Delay Line Controller Clock (5 MHz) EN_MUXCLK_Delay_Line Reset EN_CALIB_Delay_Line Load_Again Clock_to_Delay_Line(2.5MHz) OR TC Load (Asynchronous) Select_Delay_Line Count 8 Enable Constant MUX MUXCLK_Delay_Value Shift Register 8 bits Serial_Data_to_Delay_Line CALIB_Delay_Value Preshower Collaboration Meeting, 28th Nov 2002

16. Program Delay Line Controller Reset = ‘1’ s0 Select_Delay_Line = 0 s1 Load_Shift_Register = ‘1’ IF (Select_Delay_Line = 0) THEN EN_MUXCLK_Delay_Line = ‘1’ ELSE EN_CALIB_Delay_Line ‘1’ Count_8_TC = ‘0’ s2 Select_Delay_Line = 1 Load_Again = ‘1’ IF Select_Delay_Line = 0 THEN EN_MUXCLK_Delay_Line = ‘1’ ELSE EN_CALIB_Delay_Line ‘1’ & Clock_to_Delay_Line = ‘1’ s3 Count_8_TC = ‘1’ s4 Select_Delay_Line + + Select_Delay_Line != 1 s5 Load_Again = ‘0’ Preshower Collaboration Meeting, 28th Nov 2002

17. PRESHOWER System Test Block Diagram Mother Board Prototype Power LVDS MUX, PLL & CCU Control Path D O H From Last CCU 2.5V, 5VA, 5VD To Next CCU I2C SDDU x4 Isolators & LVDS Drivers G O H PACE Micro Module FPGA1 x4 ~100m ADC x4 PACE Micro Module FPGA2 G O H Isolators & LVDS Drivers SDDU x4 ADC Connector I2C JTAG Programming and M16C Interface(to FPGA) JTAG Board 40MHz OSC M16C Module RS232 to PC JTAG Power Preshower Collaboration Meeting, 28th Nov 2002